sys/arch/luna88k/dev/lunaws.c

175

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna88k/dev/siotty.c

152

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna88k/dev/siotty.c

384

sc->sc_wr[WR3] &= 0x3f;

sys/arch/luna88k/dev/siotty.c

388

sc->sc_wr[WR3] |= WR3_RX7BIT; sc->sc_wr[WR5] |= WR5_TX7BIT;

sys/arch/luna88k/dev/siotty.c

391

sc->sc_wr[WR3] |= WR3_RX8BIT; sc->sc_wr[WR5] |= WR5_TX8BIT;

sys/arch/luna88k/dev/siotty.c

404

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna88k/dev/siotty.c

670

setsioreg(sio, WR3, ch0_regs[WR3]);

sys/arch/luna88k/stand/boot/sio.c

211

sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */

sys/arch/luna88k/stand/boot/sio.c

220

sioreg(REG(1, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */