sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

434

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

435

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

436

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

437

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

438

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

470

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

471

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

472

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

473

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

474

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

666

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

667

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

668

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

669

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

670

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

430

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

431

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

432

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

433

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

434

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

396

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

397

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

398

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

399

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

400

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

914

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

915

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

916

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

917

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

918

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1376

table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2198

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2200

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2202

table->WatermarkRow[WM_SOCCLK][i].MinUclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2204

table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2207

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1900

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1902

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1904

table->WatermarkRow[WM_SOCCLK][i].MinUclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1906

table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1909

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1628

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1630

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1632

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1634

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1637

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1090

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1092

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1094

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1096

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1099

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1101

table->WatermarkRow[WM_SOCCLK][i].WmType =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

692

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

694

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

696

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

698

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

701

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

438

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

440

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

442

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

444

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

447

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

529

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

531

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

533

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

535

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

538

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

511

table->WatermarkRow[WM_SOCCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

513

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

515

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

517

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

520

table->WatermarkRow[WM_SOCCLK][i].WmSetting =