sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

363

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

400

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

554

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

591

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

323

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

360

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

289

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

326

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

784

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

821

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1420

ranges.reader_wm_sets[2].wm_inst = WM_C;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2302

table_entry = &bw_params->wm_table.entries[WM_C];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

786

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

823

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

860

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

897

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

934

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

971

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

408

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

436

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

437

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

691

base->bw_params->wm_table.nv_entries[WM_C].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

692

base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

693

base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

694

base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

695

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

696

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

697

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

698

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

699

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

237

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

274

.wm_inst = WM_C,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

451

table_entry = &bw_params->wm_table.entries[WM_C];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

236

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

237

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

238

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

239

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

240

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

241

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

242

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

243

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

244

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

245

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2508

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2536

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2537

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2538

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2556

if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {