sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

397

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

398

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

400

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

401

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

403

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

405

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

408

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

411

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

416

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

417

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

420

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

428

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

429

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

430

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

431

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

433

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

434

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

436

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

437

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

439

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

441

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

444

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

447

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

452

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

453

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

456

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

464

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

465

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

466

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

467

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

629

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

630

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

632

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

633

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

635

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

637

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

640

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

643

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

648

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

649

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

652

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

660

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

661

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

662

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

663

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

393

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

394

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

396

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

397

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

399

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

401

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

404

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

407

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

412

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

413

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

416

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

424

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

425

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

426

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

427

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

359

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

360

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

362

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

363

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

365

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

367

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

370

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

373

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

378

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

379

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

382

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

390

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

391

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

392

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

393

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

877

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

878

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

880

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

881

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

883

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

885

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

888

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

891

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

896

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

897

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

900

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

908

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

909

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

910

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

911

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1373

table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1614

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1616

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1618

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1620

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1623

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1074

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1076

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1078

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1080

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1083

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1085

table->WatermarkRow[WM_DCFCLK][i].WmType =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

678

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

680

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

682

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

684

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

687

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

424

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

426

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

428

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

430

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

433

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

515

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

517

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

519

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

521

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

524

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

497

table->WatermarkRow[WM_DCFCLK][i].MinClock =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

499

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

501

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

503

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

506

table->WatermarkRow[WM_DCFCLK][i].WmSetting =