sys/dev/mii/atphy.c

185

bmcr = BMCR_S100;

sys/dev/mii/brgphy.c

290

BMCR_S100);

sys/dev/mii/brgphy.c

292

BMCR_S100 | BMCR_FDX);

sys/dev/mii/brgphy.c

355

speed = BMCR_S100;

sys/dev/mii/ciphy.c

183

speed = BMCR_S100;

sys/dev/mii/dcphy.c

155

sc->mii_inst), BMCR_LOOP|BMCR_S100);

sys/dev/mii/exphy.c

205

PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_AUTOEN|BMCR_FDX);

sys/dev/mii/icsphy.c

271

PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_AUTOEN|BMCR_FDX);

sys/dev/mii/ipgphy.c

179

speed = BMCR_S100;

sys/dev/mii/mii_physubr.c

64

{ BMCR_S100, ANAR_CSMA|ANAR_T4, 0 },

sys/dev/mii/mii_physubr.c

66

{ BMCR_S100, ANAR_CSMA|ANAR_TX, 0 },

sys/dev/mii/mii_physubr.c

68

{ BMCR_S100|BMCR_FDX, ANAR_CSMA|ANAR_TX_FD, 0 },

sys/dev/mii/rgephy.c

197

speed = BMCR_S100;

sys/dev/sbus/be.c

1421

bmcr |= BMCR_S100;

sys/dev/sbus/be.c

1423

bmcr &= ~BMCR_S100;

sys/dev/sbus/be.c

1426

bmcr &= ~BMCR_S100;

sys/dev/sbus/be.c

1478

sc->sc_intphy_curspeed = (bmcr & BMCR_S100);

sys/dev/sbus/be.c

1487

(bmcr & BMCR_S100) ? "100" : "10");

sys/dev/sbus/be.c

1507

bmcr ^= BMCR_S100;

sys/dev/sbus/be.c

1549

switch (bmcr & (BMCR_S100 | BMCR_FDX)) {

sys/dev/sbus/be.c

1550

case (BMCR_S100 | BMCR_FDX):

sys/dev/sbus/be.c

1553

case BMCR_S100:

sys/dev/sbus/be.c

408

BMCR_S100, NULL);