sys/dev/mii/atphy.c

222

PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |

sys/dev/mii/atphy.c

371

if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)

sys/dev/mii/atphy.c

400

PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);

sys/dev/mii/jmphy.c

275

PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);

sys/dev/mii/jmphy.c

279

if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)

sys/dev/mii/mii_physubr.c

287

reg = BMCR_RESET;

sys/dev/mii/mii_physubr.c

289

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/mii_physubr.c

305

if ((reg & BMCR_RESET) == 0)

sys/dev/pci/if_age.c

578

age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);

sys/dev/pci/if_age.c

598

BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);

sys/dev/pci/if_rge.c

1050

rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |

sys/dev/pci/if_rge.c

1989

rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |

sys/dev/pci/if_rge.c

1992

if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))

sys/dev/pci/if_sk.c

1977

SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET);

sys/dev/pci/if_tl.c

849

while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);

sys/dev/sbus/be.c

1288

be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);

sys/dev/sbus/be.c

1292

if ((bmcr & BMCR_RESET) == 0)