BMCR_RESET
PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);
if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
reg = BMCR_RESET;
reg = BMCR_RESET | BMCR_ISO;
if ((reg & BMCR_RESET) == 0)
age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))
SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET);
while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
if ((bmcr & BMCR_RESET) == 0)