sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3163

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3165

v->VREADY_AT_OR_AFTER_VSYNC[k] = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3178

dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3181

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3183

v->VREADY_AT_OR_AFTER_VSYNC[k] = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3196

dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1458

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1460

v->VREADY_AT_OR_AFTER_VSYNC[k] = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1475

v->VREADY_AT_OR_AFTER_VSYNC[k]);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

182

dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h

1169

bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10318

dml_get_per_surface_var_func(vready_at_or_after_vsync, dml_uint_t, mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9714

locals->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9716

locals->VREADY_AT_OR_AFTER_VSYNC[k] = false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9731

dml_print("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, locals->VREADY_AT_OR_AFTER_VSYNC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1192

dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11882

mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11884

mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11898

DML_LOG_VERBOSE("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12457

l->vready_after_vcount0 = (unsigned int)(mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[mode_lib->mp.pipe_plane[pipe_idx]]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13225

out->informative.misc.vready_at_or_after_vsync[k] = mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

893

bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];