sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

325

u64 VM_L2_CNTL2;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

191

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

192

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

242

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

243

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

554

adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

589

WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

643

tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

644

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

861

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

862

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

177

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

178

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

219

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

220

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

292

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

294

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

sys/dev/pci/drm/radeon/cik.c

5445

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/pci/drm/radeon/cik.c

5562

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/evergreen.c

2416

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/evergreen.c

2469

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/evergreen.c

2499

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/ni.c

1274

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/pci/drm/radeon/ni.c

1353

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/r600.c

1145

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/r600.c

1237

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/rv770.c

910

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/rv770.c

956

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/rv770.c

987

WREG32(VM_L2_CNTL2, 0);

sys/dev/pci/drm/radeon/si.c

4291

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/pci/drm/radeon/si.c

4377

WREG32(VM_L2_CNTL2, 0);