Symbol: VM_CONTEXT0_CNTL
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
223
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
224
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
226
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
228
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
279
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
280
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
282
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
284
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
661
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
662
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
663
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
894
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
895
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
896
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
204
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
205
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
206
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
255
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
256
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
258
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
260
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
334
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
335
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
338
VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
340
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/radeon/cik.c
5456
WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/cik.c
5550
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2444
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/evergreen.c
2463
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/evergreen.c
2513
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/ni.c
1285
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/ni.c
1342
WREG32(VM_CONTEXT0_CNTL, 0);
sys/dev/pci/drm/radeon/r600.c
1171
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/r600.c
1176
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/r600.c
1193
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/r600.c
1259
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
1002
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
929
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/rv770.c
934
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/rv770.c
951
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
sys/dev/pci/drm/radeon/si.c
4302
WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
sys/dev/pci/drm/radeon/si.c
4367
WREG32(VM_CONTEXT0_CNTL, 0);