sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

907

VMID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

921

VMID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

51

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

561

return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

45

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

837

VMID,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6158

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6236

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6313

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6780

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6787

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6963

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2516

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2560

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2635

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2716

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2757

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2839

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2875

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2881

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3246

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3327

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3464

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3546

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3969

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3975

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4104

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4111

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4285

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2410

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2464

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2554

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2609

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2864

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2870

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2981

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2988

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3163

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4442

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3496

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3614

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1773

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1893

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

616

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1291

VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

772

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1006

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1479

VMID);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1143

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1219

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1234

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1303

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1386

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1401

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/nv.c

323

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc15.c

369

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc21.c

244

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/soc24.c

107

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

84

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/amd/amdgpu/vi.c

584

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

739

VMID, address->vmid);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

116

HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

204

type VMID

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

606

VMID, flip_regs->vmid);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

91

HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

82

VMID, address->vmid);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

239

HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

224

HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

423

VMID, address->vmid);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

211

HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

200

tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

sys/dev/pci/drm/radeon/cik.c

1846

VMID(vmid & 0xf) |

sys/dev/pci/drm/radeon/cik.c

5701

radeon_ring_write(ring, VMID(vm_id));

sys/dev/pci/drm/radeon/cik.c

5719

radeon_ring_write(ring, VMID(0));

sys/dev/pci/drm/radeon/cik_sdma.c

961

radeon_ring_write(ring, VMID(vm_id));

sys/dev/pci/drm/radeon/cik_sdma.c

981

radeon_ring_write(ring, VMID(0));

usr.sbin/vmd/parse.y

124

%token PATH PREFIX RDOMAIN SIZE SOCKET SWITCH UP VM VMID STAGGERED START

usr.sbin/vmd/parse.y

837

{ "id", VMID },