sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

101

#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

102

#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

111

#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

120

#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

131

#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

152

#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

175

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

24

#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

37

#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

82

#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

89

#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

98

#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

152

#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

155

#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

161

#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \

sys/dev/pci/drm/i915/display/intel_audio_regs.h

41

#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

42

#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

44

#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

45

#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

47

#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

55

#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

56

#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

11

#define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

12

#define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

15

#define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

16

#define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

19

#define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

20

#define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)

sys/dev/pci/drm/i915/display/intel_color_regs.h

272

#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)

sys/dev/pci/drm/i915/display/intel_color_regs.h

273

#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)

sys/dev/pci/drm/i915/display/intel_color_regs.h

274

#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)

sys/dev/pci/drm/i915/display/intel_color_regs.h

275

#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)

sys/dev/pci/drm/i915/display/intel_color_regs.h

276

#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)

sys/dev/pci/drm/i915/display/intel_color_regs.h

277

#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)

sys/dev/pci/drm/i915/display/intel_color_regs.h

283

#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)

sys/dev/pci/drm/i915/display/intel_color_regs.h

289

#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)

sys/dev/pci/drm/i915/display/intel_color_regs.h

294

#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)

sys/dev/pci/drm/i915/display/intel_color_regs.h

295

#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)

sys/dev/pci/drm/i915/display/intel_color_regs.h

296

#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)

sys/dev/pci/drm/i915/display/intel_color_regs.h

297

#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)

sys/dev/pci/drm/i915/display/intel_color_regs.h

298

#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)

sys/dev/pci/drm/i915/display/intel_color_regs.h

299

#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)

sys/dev/pci/drm/i915/display/intel_color_regs.h

300

#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)

sys/dev/pci/drm/i915/display/intel_color_regs.h

301

#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

13

#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)

sys/dev/pci/drm/i915/display/intel_display_device.c

528

.mmio_offset = VLV_DISPLAY_BASE,

sys/dev/pci/drm/i915/display/intel_display_device.c

649

.mmio_offset = VLV_DISPLAY_BASE,

sys/dev/pci/drm/i915/display/intel_display_regs.h

13

#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)

sys/dev/pci/drm/i915/display/intel_display_regs.h

164

#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)

sys/dev/pci/drm/i915/display/intel_display_regs.h

166

#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

177

#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1906

#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1914

#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1922

#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2090

#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

263

#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)

sys/dev/pci/drm/i915/display/intel_display_regs.h

280

#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)

sys/dev/pci/drm/i915/display/intel_display_regs.h

283

#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)

sys/dev/pci/drm/i915/display/intel_display_regs.h

285

#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)

sys/dev/pci/drm/i915/display/intel_display_regs.h

290

#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

297

#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)

sys/dev/pci/drm/i915/display/intel_display_regs.h

506

#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)

sys/dev/pci/drm/i915/display/intel_display_regs.h

507

#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)

sys/dev/pci/drm/i915/display/intel_display_regs.h

508

#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

632

#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)

sys/dev/pci/drm/i915/display/intel_display_regs.h

633

#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)

sys/dev/pci/drm/i915/display/intel_display_regs.h

634

#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)

sys/dev/pci/drm/i915/display/intel_display_regs.h

86

#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

87

#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

88

#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)

sys/dev/pci/drm/i915/display/intel_display_regs.h

885

#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */

sys/dev/pci/drm/i915/display/intel_display_regs.h

915

#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)

sys/dev/pci/drm/i915/display/intel_display_regs.h

919

#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

28

#define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \

sys/dev/pci/drm/i915/display/intel_dp_aux_regs.h

82

#define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \

sys/dev/pci/drm/i915/display/intel_gmbus.c

1022

display->gmbus.mmio_base = VLV_DISPLAY_BASE;

sys/dev/pci/drm/i915/display/intel_pps_regs.h

13

#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

235

#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

236

#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

264

#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

265

#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

268

#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

269

#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

272

#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

273

#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

280

#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

281

#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

288

#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

289

#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

292

#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

293

#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

296

#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

297

#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

301

#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

302

#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

305

#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

306

#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

313

#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

314

#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

320

#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

321

#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

324

#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

325

#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

332

#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

333

#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

340

#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

341

#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

352

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/pci/drm/i915/display/intel_vga_regs.h

12

#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

11

#define VLV_MIPI_BASE VLV_DISPLAY_BASE

sys/dev/pci/drm/i915/i915_reg.h

158

#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)

sys/dev/pci/drm/i915/i915_reg.h

180

#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)

sys/dev/pci/drm/i915/i915_reg.h

181

#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)

sys/dev/pci/drm/i915/i915_reg.h

357

#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)

sys/dev/pci/drm/i915/i915_reg.h

362

#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)

sys/dev/pci/drm/i915/i915_reg.h

363

#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)

sys/dev/pci/drm/i915/i915_reg.h

376

#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)

sys/dev/pci/drm/i915/i915_reg.h

379

#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)

sys/dev/pci/drm/i915/i915_reg.h

380

#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)

sys/dev/pci/drm/i915/i915_reg.h

381

#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)

sys/dev/pci/drm/i915/i915_reg.h

382

#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)

sys/dev/pci/drm/i915/i915_reg.h

383

#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)

sys/dev/pci/drm/i915/i915_reg.h

384

#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)

sys/dev/pci/drm/i915/i915_reg.h

385

#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)

sys/dev/pci/drm/i915/i915_reg.h

617

#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)

sys/dev/pci/drm/i915/i915_reg.h

774

#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)