sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3259

tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);

sys/dev/pci/drm/radeon/cik.c

7323

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/cik.c

7327

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/cik.c

7339

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/cik.c

7343

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/cik.c

7356

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/cik.c

7360

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

4639

VLINE_ACK);

sys/dev/pci/drm/radeon/si.c

6154

VLINE_ACK);