sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

51

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

784

JPEG_HWIP = VCN_HWIP,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2541

switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

37

case VCN_HWIP:

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

87

{ VCN_HWIP, adev->vcn.inst_mask },

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3888

if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3889

amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3890

amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3891

amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 0, 1))

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

126

switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

318

switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

202

uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

45

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

42

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

258

if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) {

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

306

IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

64

if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2211

switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

161

if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2042

if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2327

switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1528

if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5))

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

43

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));