BL3
#define OSIOP_DCMD (0x24+BL3) /* rw: DMA Command Register */
#define OSIOP_DCNTL (0x38+BL3) /* rw: DMA Control reg */
#define OSIOP_SIEN (0x00+BL3) /* rw: SCSI interrupt enable */
#define OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */
#define OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */
#define OSIOP_SSTAT2 (0x0c+BL3) /* ro: SCSI status reg 2 */
#define OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */
#define OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */
#define OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */