BL1
#define OSIOP_DIEN (0x38+BL1) /* rw: DMA Interrupt Enable */
#define OSIOP_SCNTL1 (0x00+BL1) /* rw: SCSI control reg 1 */
#define OSIOP_SXFER (0x04+BL1) /* rw: SCSI Transfer reg */
#define OSIOP_SIDL (0x08+BL1) /* ro: SCSI Input Data Latch */
#define OSIOP_SSTAT0 (0x0c+BL1) /* ro: SCSI status reg 0 */
#define OSIOP_CTEST1 (0x14+BL1) /* ro: Chip test register 1 */
#define OSIOP_CTEST5 (0x18+BL1) /* rw: Chip test register 5 */
#define OSIOP_ISTAT (0x20+BL1) /* rw: Interrupt Status reg */
#define OSIOP_DBC1 (0x24+BL1) /* rw: DMA Byte Counter reg 1 */