sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

459

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

461

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

410

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

412

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

289

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

464

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2208

WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

sys/dev/pci/drm/radeon/evergreen.c

2670

save->vga_render_control = RREG32(VGA_RENDER_CONTROL);

sys/dev/pci/drm/radeon/evergreen.c

2674

WREG32(VGA_RENDER_CONTROL, 0);

sys/dev/pci/drm/radeon/evergreen.c

2845

WREG32(VGA_RENDER_CONTROL, save->vga_render_control);