sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2461

[I915_EXEC_VEBOX] = VECS0

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

179

case VECS0:

sys/dev/pci/drm/i915/gt/intel_engine.h

101

ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1717

[VECS0] = MSG_IDLE_VECS0,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

193

[VECS0] = {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

420

[VECS0] = GEN11_GRDOM_VECS,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

439

[VECS0] = GEN6_GRDOM_VECS,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

214

[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3506

[VECS0] = GEN8_VECS_IRQ_SHIFT,

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

550

if (HAS_ENGINE(gt, VECS0)) {

sys/dev/pci/drm/i915/gt/intel_mocs.c

572

[VECS0] = __GEN9_VECS0_MOCS0,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

104

case VECS0:

sys/dev/pci/drm/i915/gt/intel_rps.c

1953

intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1175

[VECS0] = {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

433

#define R_VECS BIT(VECS0)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

633

[VECS0] = {

sys/dev/pci/drm/i915/gvt/execlist.c

53

[VECS0] = VECS_AS_CONTEXT_SWITCH,

sys/dev/pci/drm/i915/gvt/handlers.c

2116

id = VECS0;

sys/dev/pci/drm/i915/gvt/handlers.c

352

engine_mask |= BIT(VECS0);

sys/dev/pci/drm/i915/gvt/mmio_context.c

145

{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

173

[VECS0] = 0xcb00,

sys/dev/pci/drm/i915/gvt/mmio_context.c

360

[VECS0] = 0x4270,

sys/dev/pci/drm/i915/gvt/mmio_context.c

417

[VECS0] = 0xcb00,

sys/dev/pci/drm/i915/i915_gpu_error.c

1426

case VECS0:

sys/dev/pci/drm/i915/i915_pci.c

388

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

447

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

453

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

498

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)

sys/dev/pci/drm/i915/i915_pci.c

513

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

560

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

581

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

614

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

620

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

627

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

643

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

650

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),

sys/dev/pci/drm/i915/i915_pci.c

667

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |

sys/dev/pci/drm/i915/i915_pci.c

677

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

685

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

735

BIT(VECS0) | BIT(VECS1) | \

sys/dev/pci/drm/i915/i915_pci.c

755

.engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),