regress/sys/arch/amd64/vmm/vcpu.c

69

.vrs_sregs[VCPU_REGS_TR] = { 0x0, 0xFFFF, 0x008B, 0x0},

sys/arch/amd64/amd64/vmm_machdep.c

1223

sregs[VCPU_REGS_TR].vsi_sel = vmcb->v_tr.vs_sel;

sys/arch/amd64/amd64/vmm_machdep.c

1224

sregs[VCPU_REGS_TR].vsi_limit = vmcb->v_tr.vs_lim;

sys/arch/amd64/amd64/vmm_machdep.c

1226

sregs[VCPU_REGS_TR].vsi_ar = (attr & 0xff) | ((attr << 4) &

sys/arch/amd64/amd64/vmm_machdep.c

1228

sregs[VCPU_REGS_TR].vsi_base = vmcb->v_tr.vs_base;

sys/arch/amd64/amd64/vmm_machdep.c

1498

vmcb->v_tr.vs_sel = sregs[VCPU_REGS_TR].vsi_sel;

sys/arch/amd64/amd64/vmm_machdep.c

1499

vmcb->v_tr.vs_lim = sregs[VCPU_REGS_TR].vsi_limit;

sys/arch/amd64/amd64/vmm_machdep.c

1500

attr = sregs[VCPU_REGS_TR].vsi_ar;

sys/arch/amd64/amd64/vmm_machdep.c

1502

vmcb->v_tr.vs_base = sregs[VCPU_REGS_TR].vsi_base;

sys/arch/amd64/include/vmmvar.h

424

#define VCPU_REGS_NSREGS (VCPU_REGS_TR + 1)

usr.sbin/vmd/x86_mmio.c

360

case VCPU_REGS_TR: return "TR";

usr.sbin/vmd/x86_vm.c

131

.vrs_sregs[VCPU_REGS_TR] = { 0x0, 0xFFFF, 0x008B, 0x0},

usr.sbin/vmd/x86_vm.c

95

.vrs_sregs[VCPU_REGS_TR] = { 0x0, 0xFFFF, 0x008B, 0x0},