sys/arch/amd64/amd64/vmm_machdep.c

2404

msr_store[VCPU_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE;

sys/arch/amd64/amd64/vmm_machdep.c

2410

msr_store[VCPU_REGS_MISC_ENABLE].vms_data = msr_misc_enable;

sys/arch/amd64/amd64/vmm_machdep.c

2411

msr_store[VCPU_REGS_MISC_ENABLE].vms_data &=

sys/arch/amd64/amd64/vmm_machdep.c

2415

msr_store[VCPU_REGS_MISC_ENABLE].vms_data |=

sys/arch/amd64/amd64/vmm_machdep.c

6008

msr_store[VCPU_REGS_MISC_ENABLE].vms_data = *rax | (*rdx << 32);

sys/arch/amd64/amd64/vmm_machdep.c

6304

if (msr_store[VCPU_REGS_MISC_ENABLE].vms_data &

sys/arch/amd64/include/vmmvar.h

433

#define VCPU_REGS_NMSRS (VCPU_REGS_MISC_ENABLE + 1)

usr.sbin/vmd/x86_vm.c

108

.vrs_msrs[VCPU_REGS_MISC_ENABLE] = 0ULL,