sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1196

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1428

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1436

ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1437

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

932

if (status & UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

937

if (status & UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1230

r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1383

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1391

ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1392

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1599

r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1961

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1975

ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1976

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1648

r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2223

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2238

ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2239

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2260

if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1625

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2067

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2089

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2090

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2120

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1416

UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1693

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1713

UVD_STATUS__IDLE, UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1740

regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1288

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1552

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1574

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1575

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1605

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1019

r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1273

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1295

ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1296

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1326

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1189

r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1393

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1411

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1412

UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1439

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)