sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1521

offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

279

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

253

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

298

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

303

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

337

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

231

uint8_t UvdBootLevel;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2012

table->UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2872

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2874

smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2877

UvdBootLevel, smu_data->smc_state_table.UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1565

table->UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2326

case UvdBootLevel:

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2327

return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2372

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2374

smu_data->smc_state_table.UvdBootLevel =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2377

UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2383

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2393

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1534

table->UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2288

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2290

smu_data->smc_state_table.UvdBootLevel =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2293

UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2299

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2309

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2451

case UvdBootLevel:

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2452

return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1321

table->UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2637

case UvdBootLevel:

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2638

return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2683

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2685

smu_data->smc_state_table.UvdBootLevel =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2688

offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2694

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2705

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1321

table->UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2186

case UvdBootLevel:

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2187

return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

337

smu_data->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

339

smu_data->smc_state_table.UvdBootLevel =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

342

UvdBootLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

348

mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

358

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/radeon/ci_dpm.c

3572

table->UvdBootLevel = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4035

pi->smc_state_table.UvdBootLevel = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

4037

pi->smc_state_table.UvdBootLevel =

sys/dev/pci/drm/radeon/ci_dpm.c

4042

tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);

sys/dev/pci/drm/radeon/kv_dpm.c

1265

offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),

sys/dev/pci/drm/radeon/smu7_discrete.h

323

uint8_t UvdBootLevel;

sys/dev/pci/drm/radeon/smu7_fusion.h

231

uint8_t UvdBootLevel;