sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

421

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

422

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

423

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

424

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

425

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

426

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

839

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

840

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

841

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

842

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

843

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

844

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

865

WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1086

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1087

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1088

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1089

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1090

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1091

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

919

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

920

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1134

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1135

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1136

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1137

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1138

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

970

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

971

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

972

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

973

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

974

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1132

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1133

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1134

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1135

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1136

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2078

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2079

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2080

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2081

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2082

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

953

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

954

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

955

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

956

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

957

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1114

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1115

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1116

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1117

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1118

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1304

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1305

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1306

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1307

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1308

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1527

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1528

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1529

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1530

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1531

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1139

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1140

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1141

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1142

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1143

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1330

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1331

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1332

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1333

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1334

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1520

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1521

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1522

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1523

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1524

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

sys/dev/pci/drm/radeon/uvd_v1_0.c

358

WREG32(UVD_RBC_RB_CNTL, 0x11010101);

sys/dev/pci/drm/radeon/uvd_v1_0.c

379

WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);

sys/dev/pci/drm/radeon/uvd_v1_0.c

394

WREG32(UVD_RBC_RB_CNTL, 0x11010101);