sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1326

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1355

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1313

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1360

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1681

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1723

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1736

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1787

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1719

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1732

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1382

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1396

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1110

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1120

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

639

reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

648

reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;