sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

526

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

651

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

653

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

714

reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

716

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

554

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

657

reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

659

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

716

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

718

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

767

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

874

reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

876

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

933

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

935

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

787

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

918

reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

920

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

975

data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

977

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

866

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

922

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

751

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

804

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

804

reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

860

data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;