sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

216

(1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

645

(1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

530

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

654

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

717

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

557

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

660

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

719

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

770

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

877

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

936

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

790

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

921

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

978

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

752

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

867

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

923

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

658

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

752

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

805

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

690

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

805

reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

861

data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;