sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

50

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

66

[UMC_HWIP] = "UMC",

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

236

[UMC_HWIP] = UMC_HWID,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2598

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2627

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2657

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2674

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2704

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2741

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2773

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2806

adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

224

if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2351

if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2957

if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3155

if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3667

if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) >= 12 &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4002

amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(12, 0, 0))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

419

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

741

if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

227

if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

35

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

54

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

579

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

569

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

605

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1417

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1528

switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1657

(amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

526

if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

52

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));