UINT32_C
#define BN_DEC_CONV UINT32_C(1000000000)
#define BN_MASK2 UINT32_C(0xffffffff)
#define BN_MASK2l UINT32_C(0xffff)
#define BN_MASK2h UINT32_C(0xffff0000)
#define USBC_GOTGCTL_XXX_20 UINT32_C(0x00100000)
#define USBC_GOTGCTL_BSESVLD UINT32_C(0x00080000)
#define USBC_GOTGCTL_ASESVLD UINT32_C(0x00040000)
#define USBC_GOTGCTL_DBNCTIME UINT32_C(0x00020000)
#define USBC_GOTGCTL_CONIDSTS UINT32_C(0x00010000)
#define USBC_GOTGCTL_DEVHNPEN UINT32_C(0x00000800)
#define USBC_GOTGCTL_HSTSETHNPEN UINT32_C(0x00000400)
#define USBC_GOTGCTL_HNPREQ UINT32_C(0x00000200)
#define USBC_GOTGCTL_HSTNEGSCS UINT32_C(0x00000100)
#define USBC_GOTGCTL_SESREQ UINT32_C(0x00000002)
#define USBC_GOTGCTL_SESREQSCS UINT32_C(0x00000001)
#define USBC_GOTGINT_DBNCEDONE UINT32_C(0x00080000)
#define USBC_GOTGINT_ADEVTOUTCHG UINT32_C(0x00040000)
#define USBC_GOTGINT_HSTNEGDET UINT32_C(0x00020000)
#define USBC_GOTGINT_HSTNEGSUCSTSCHNG UINT32_C(0x00000200)
#define USBC_GOTGINT_SESREQSUCSTSCHNG UINT32_C(0x00000100)
#define USBC_GOTGINT_SESENDDET UINT32_C(0x00000004)
#define USBC_GOTGINT_XXX_1 UINT32_C(0x00000002)
#define USBC_GOTGINT_XXX_0 UINT32_C(0x00000001)
#define USBC_GAHBCFG_PTXFEMPLVL UINT32_C(0x00000100)
#define USBC_GAHBCFG_NPTXFEMPLVL UINT32_C(0x00000080)
#define USBC_GAHBCFG_XXX_6 UINT32_C(0x00000040)
#define USBC_GAHBCFG_DMAEN UINT32_C(0x00000020)
#define USBC_GAHBCFG_GLBLINTRMSK UINT32_C(0x00000001)
#define USBC_GUSBCFG_OTGI2CSEL UINT32_C(0x00010000)
#define USBC_GUSBCFG_PHYLPWRCLKSEL UINT32_C(0x00008000)
#define USBC_GUSBCFG_XXX_14 UINT32_C(0x00004000)
#define USBC_GUSBCFG_HNPCAP UINT32_C(0x00000200)
#define USBC_GUSBCFG_SRPCAP UINT32_C(0x00000100)
#define USBC_GUSBCFG_DDRSEL UINT32_C(0x00000080)
#define USBC_GUSBCFG_PHYSEL UINT32_C(0x00000040)
#define USBC_GUSBCFG_FSINTF UINT32_C(0x00000020)
#define USBC_GUSBCFG_ULPI_UTMI_SEL UINT32_C(0x00000010)
#define USBC_GUSBCFG_PHYIF UINT32_C(0x00000008)
#define USBC_GRSTCTL_AHBIDLE UINT32_C(0x80000000)
#define USBC_GRSTCTL_DMAREQ UINT32_C(0x40000000)
#define USBC_GRSTCTL_TXFFLSH UINT32_C(0x00000020)
#define USBC_GRSTCTL_RXFFLSH UINT32_C(0x00000010)
#define USBC_GRSTCTL_INTKNQFLSH UINT32_C(0x00000008)
#define USBC_GRSTCTL_FRMCNTRRST UINT32_C(0x00000004)
#define USBC_GRSTCTL_HSFTRST UINT32_C(0x00000002)
#define USBC_GRSTCTL_CSFTRST UINT32_C(0x00000001)
#define USBC_GINTSTS_WKUPINT UINT32_C(0x80000000)
#define USBC_GINTSTS_SESSREQINT UINT32_C(0x40000000)
#define USBC_GINTSTS_DISCONNINT UINT32_C(0x20000000)
#define USBC_GINTSTS_CONIDSTSCHNG UINT32_C(0x10000000)
#define USBC_GINTSTS_XXX_27 UINT32_C(0x08000000)
#define USBC_GINTSTS_PTXFEMP UINT32_C(0x04000000)
#define USBC_GINTSTS_HCHINT UINT32_C(0x02000000)
#define USBC_GINTSTS_PRTINT UINT32_C(0x01000000)
#define USBC_GINTSTS_XXX_23 UINT32_C(0x00800000)
#define USBC_GINTSTS_FETSUSP UINT32_C(0x00400000)
#define USBC_GINTSTS_INCOMPLP UINT32_C(0x00200000)
#define USBC_GINTSTS_INCOMPISOIN UINT32_C(0x00100000)
#define USBC_GINTSTS_OEPINT UINT32_C(0x00080000)
#define USBC_GINTSTS_IEPINT UINT32_C(0x00040000)
#define USBC_GINTSTS_EPMIS UINT32_C(0x00020000)
#define USBC_GINTSTS_XXX_16 UINT32_C(0x00010000)
#define USBC_GINTSTS_EOPF UINT32_C(0x00008000)
#define USBC_GINTSTS_ISOOUTDROP UINT32_C(0x00004000)
#define USBC_GINTSTS_ENUMDONE UINT32_C(0x00002000)
#define USBC_GINTSTS_USBRST UINT32_C(0x00001000)
#define USBC_GINTSTS_USBSUSP UINT32_C(0x00000800)
#define USBC_GINTSTS_ERLYSUSP UINT32_C(0x00000400)
#define USBC_GINTSTS_I2CINT UINT32_C(0x00000200)
#define USBC_GINTSTS_ULPICKINT UINT32_C(0x00000100)
#define USBC_GINTSTS_GOUTNAKEFF UINT32_C(0x00000080)
#define USBC_GINTSTS_GINNAKEFF UINT32_C(0x00000040)
#define USBC_GINTSTS_NPTXFEMP UINT32_C(0x00000020)
#define USBC_GINTSTS_RXFLVL UINT32_C(0x00000010)
#define USBC_GINTSTS_SOF UINT32_C(0x00000008)
#define USBC_GINTSTS_OTGINT UINT32_C(0x00000004)
#define USBC_GINTSTS_MODEMIS UINT32_C(0x00000002)
#define USBC_GINTSTS_CURMOD UINT32_C(0x00000001)
#define USBC_GINTMSK_WKUPINTMSK UINT32_C(0x80000000)
#define USBC_GINTMSK_SESSREQINTMSK UINT32_C(0x40000000)
#define USBC_GINTMSK_DISCONNINTMSK UINT32_C(0x20000000)
#define USBC_GINTMSK_CONIDSTSTCHNGMSK UINT32_C(0x10000000)
#define USBC_GINTMSK_XXX_27 UINT32_C(0x08000000)
#define USBC_GINTMSK_PTXFEMPMSK UINT32_C(0x04000000)
#define USBC_GINTMSK_HCHINTMSK UINT32_C(0x02000000)
#define USBC_GINTMSK_PRTINTMSK UINT32_C(0x01000000)
#define USBC_GINTMSK_XXX_23 UINT32_C(0x00800000)
#define USBC_GINTMSK_FETSUSPMSK UINT32_C(0x00400000)
#define USBC_GINTMSK_INCOMPISOOUTMSK UINT32_C(0x00200000)
#define USBC_GINTMSK_INCOMPISOINMSK UINT32_C(0x00100000)
#define USBC_GINTMSK_OEPINTMSK UINT32_C(0x00080000)
#define USBC_GINTMSK_INEPINTMSK UINT32_C(0x00040000)
#define USBC_GINTMSK_EPMISMSK UINT32_C(0x00020000)
#define USBC_GINTMSK_XXX_16 UINT32_C(0x00010000)
#define USBC_GINTMSK_EOPFMSK UINT32_C(0x00008000)
#define USBC_GINTMSK_ISOOUTDROPMSK UINT32_C(0x00004000)
#define USBC_GINTMSK_ENUMDONEMSK UINT32_C(0x00002000)
#define USBC_GINTMSK_USBRSTMSK UINT32_C(0x00001000)
#define USBC_GINTMSK_USBSUSPMSK UINT32_C(0x00000800)
#define USBC_GINTMSK_ERLYSUSPMSK UINT32_C(0x00000400)
#define USBC_GINTMSK_I2CINT UINT32_C(0x00000200)
#define USBC_GINTMSK_ULPICKINTMSK UINT32_C(0x00000100)
#define USBC_GINTMSK_GOUTNAKEFFMSK UINT32_C(0x00000080)
#define USBC_GINTMSK_GINNAKEFFMSK UINT32_C(0x00000040)
#define USBC_GINTMSK_NPTXFEMPMSK UINT32_C(0x00000020)
#define USBC_GINTMSK_RXFLVLMSK UINT32_C(0x00000010)
#define USBC_GINTMSK_SOFMSK UINT32_C(0x00000008)
#define USBC_GINTMSK_OTGINTMSK UINT32_C(0x00000004)
#define USBC_GINTMSK_MODEMISMSK UINT32_C(0x00000002)
#define USBC_GINTMSK_XXX_0 UINT32_C(0x00000001)
#define USBC_GNPTXSTS_XXX_31 UINT32_C(0x80000000)
#define USBC_GNPTXSTS_NPTXQTOP_TERMINATE UINT32_C(0x01000000)
#define USBC_GHWCFG2_XXX_31 UINT32_C(0x80000000)
#define USBC_GHWCFG2_DYNFIFOSIZING UINT32_C(0x00080000)
#define USBC_GHWCFG2_PERIOSUPPORT UINT32_C(0x00040000)
#define USBC_GHWCFG2_SINGPNT UINT32_C(0x00000020)
#define USBC_GHWCFG3_AHBPHYSYNC UINT32_C(0x00001000)
#define USBC_GHWCFG3_RSTTYPE UINT32_C(0x00000800)
#define USBC_GHWCFG3_OPTFEATURE UINT32_C(0x00000400)
#define USBC_GHWCFG3_VENDOR_CONTROL_INTERFACE_SUPPORT UINT32_C(0x00000200)
#define USBC_GHWCFG3_I2C_SELECTION UINT32_C(0x00000100)
#define USBC_GHWCFG3_OTGEN UINT32_C(0x00000080)
#define USBC_GHWCFG4_SESSENDFLTR UINT32_C(0x01000000)
#define USBC_GHWCFG4_BVAILDFLTR UINT32_C(0x01000000)
#define USBC_GHWCFG4_AVAILDFLTR UINT32_C(0x00800000)
#define USBC_GHWCFG4_VBUSVALIDFLTR UINT32_C(0x00400000)
#define USBC_GHWCFG4_IDDGFLTR UINT32_C(0x00200000)
#define USBC_GHWCFG4_AHBFREQ UINT32_C(0x00000020)
#define USBC_GHWCFG4_ENABLEPWROPT UINT32_C(0x00000010)
#define USBC_HCFG_FSLSSUPP UINT32_C(0x00000004)
#define USBC_HAINT_HAINT_F UINT32_C(0x00008000)
#define USBC_HAINT_HAINT_E UINT32_C(0x00004000)
#define USBC_HAINT_HAINT_D UINT32_C(0x00002000)
#define USBC_HAINT_HAINT_C UINT32_C(0x00001000)
#define USBC_HAINT_HAINT_B UINT32_C(0x00000800)
#define USBC_HAINT_HAINT_A UINT32_C(0x00000400)
#define USBC_HAINT_HAINT_9 UINT32_C(0x00000200)
#define USBC_HAINT_HAINT_8 UINT32_C(0x00000100)
#define USBC_HAINT_HAINT_7 UINT32_C(0x00000080)
#define USBC_HAINT_HAINT_6 UINT32_C(0x00000040)
#define USBC_HAINT_HAINT_5 UINT32_C(0x00000020)
#define USBC_HAINT_HAINT_4 UINT32_C(0x00000010)
#define USBC_HAINT_HAINT_3 UINT32_C(0x00000008)
#define USBC_HAINT_HAINT_2 UINT32_C(0x00000004)
#define USBC_HAINT_HAINT_1 UINT32_C(0x00000002)
#define USBC_HAINT_HAINT_0 UINT32_C(0x00000001)
#define USBC_HAINTMSK_HAINTMSK_F UINT32_C(0x00008000)
#define USBC_HAINTMSK_HAINTMSK_E UINT32_C(0x00004000)
#define USBC_HAINTMSK_HAINTMSK_D UINT32_C(0x00002000)
#define USBC_HAINTMSK_HAINTMSK_C UINT32_C(0x00001000)
#define USBC_HAINTMSK_HAINTMSK_B UINT32_C(0x00000800)
#define USBC_HAINTMSK_HAINTMSK_A UINT32_C(0x00000400)
#define USBC_HAINTMSK_HAINTMSK_9 UINT32_C(0x00000200)
#define USBC_HAINTMSK_HAINTMSK_8 UINT32_C(0x00000100)
#define USBC_HAINTMSK_HAINTMSK_7 UINT32_C(0x00000080)
#define USBC_HAINTMSK_HAINTMSK_6 UINT32_C(0x00000040)
#define USBC_HAINTMSK_HAINTMSK_5 UINT32_C(0x00000020)
#define USBC_HAINTMSK_HAINTMSK_4 UINT32_C(0x00000010)
#define USBC_HAINTMSK_HAINTMSK_3 UINT32_C(0x00000008)
#define USBC_HAINTMSK_HAINTMSK_2 UINT32_C(0x00000004)
#define USBC_HAINTMSK_HAINTMSK_1 UINT32_C(0x00000002)
#define USBC_HAINTMSK_HAINTMSK_0 UINT32_C(0x00000001)
#define USBC_HPRT_PRTPWR UINT32_C(0x00001000)
#define USBC_HPRT_XXX_9 UINT32_C(0x00000200)
#define USBC_HPRT_PRTRST UINT32_C(0x00000100)
#define USBC_HPRT_PRTSUSP UINT32_C(0x00000080)
#define USBC_HPRT_PRTRES UINT32_C(0x00000040)
#define USBC_HPRT_PRTOVRCURRCHNG UINT32_C(0x00000020)
#define USBC_HPRT_PRTOVRCURRACT UINT32_C(0x00000010)
#define USBC_HPRT_PRTENCHNG UINT32_C(0x00000008)
#define USBC_HPRT_PRTENA UINT32_C(0x00000004)
#define USBC_HPRT_PRTCONNDET UINT32_C(0x00000002)
#define USBC_HPRT_PRTCONNSTS UINT32_C(0x00000001)
#define USBC_HCCHARX_CHENA UINT32_C(0x80000000)
#define USBC_HCCHARX_CHDIS UINT32_C(0x40000000)
#define USBC_HCCHARX_ODDFRM UINT32_C(0x20000000)
#define USBC_HCCHARX_LSPDDEV UINT32_C(0x00020000)
#define USBC_HCCHARX_XXX_16 UINT32_C(0x00010000)
#define USBC_HCCHARX_EPDIR UINT32_C(0x00008000)
#define USBC_HCSPLTX_SPLTENA UINT32_C(0x80000000)
#define USBC_HCSPLTX_COMPSPLT UINT32_C(0x00010000)
#define USBC_HCINTX_DATATGLERR UINT32_C(0x00000400)
#define USBC_HCINTX_FRMOVRUN UINT32_C(0x00000200)
#define USBC_HCINTX_BBLERR UINT32_C(0x00000100)
#define USBC_HCINTX_XACTERR UINT32_C(0x00000080)
#define USBC_HCINTX_NYET UINT32_C(0x00000040)
#define USBC_HCINTX_ACK UINT32_C(0x00000020)
#define USBC_HCINTX_NAK UINT32_C(0x00000010)
#define USBC_HCINTX_STALL UINT32_C(0x00000008)
#define USBC_HCINTX_AHBERR UINT32_C(0x00000004)
#define USBC_HCINTX_CHHLTD UINT32_C(0x00000002)
#define USBC_HCINTX_XFERCOMPL UINT32_C(0x00000001)
#define USBC_HCINTMSKX_DATATGLERRMSK UINT32_C(0x00000400)
#define USBC_HCINTMSKX_FRMOVRUNMSK UINT32_C(0x00000200)
#define USBC_HCINTMSKX_BBLERRMSK UINT32_C(0x00000100)
#define USBC_HCINTMSKX_XACTERRMSK UINT32_C(0x00000080)
#define USBC_HCINTMSKX_NYETMSK UINT32_C(0x00000040)
#define USBC_HCINTMSKX_ACKMSK UINT32_C(0x00000020)
#define USBC_HCINTMSKX_NAKMSK UINT32_C(0x00000010)
#define USBC_HCINTMSKX_STALLMSK UINT32_C(0x00000008)
#define USBC_HCINTMSKX_AHBERRMSK UINT32_C(0x00000004)
#define USBC_HCINTMSKX_CHHLTDMSK UINT32_C(0x00000002)
#define USBC_HCINTMSKX_XFERCOMPLMSK UINT32_C(0x00000001)
#define USBC_HCTSIZX_DOPNG UINT32_C(0x80000000)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK UINT32_C(0xff00000)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK UINT32_C(0xffff)
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
#define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK UINT32_C(0xfffe)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (UINT32_C(0x1) << 1)
#define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (UINT32_C(0xa) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (UINT32_C(0x14) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (UINT32_C(0x19) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (UINT32_C(0x64) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (UINT32_C(0xc8) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (UINT32_C(0xfa) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (UINT32_C(0x190) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (UINT32_C(0x1f4) << 1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (UINT32_C(0x3e8) << 1)
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0000)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP UINT32_C(0x8)
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (UINT32_C(0xff) << 16)
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK UINT32_C(0xff000000)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (UINT32_C(0xff) << 24)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK UINT32_C(0xff0000)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (UINT32_C(0x0) << 16)
#define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (UINT32_C(0x1) << 16)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (UINT32_C(0x2) << 16)
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (UINT32_C(0x3) << 16)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
#define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE UINT32_C(0x10000)
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG UINT32_C(0x20000)
#define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
#define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MASK UINT32_C(0xff)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NONE UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_DISABLETX UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MISMATCH UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_PWRDOWN UINT32_C(0x3)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTINSERTED UINT32_C(0x4)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_CURRENTFAULT UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_OVERHEATED UINT32_C(0x6)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
#define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE UINT32_C(0x10000)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE UINT32_C(0x20000)
#define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE UINT32_C(0x40000)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK UINT32_C(0xffff)
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (UINT32_C(0x1) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (UINT32_C(0x2) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (UINT32_C(0x3) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (UINT32_C(0x4) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (UINT32_C(0x5) << 8)
#define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK UINT32_C(0xffff0000)
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY UINT32_C(0x9)
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK UINT32_C(0xff)
#define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED UINT32_C(0x2)
#define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG UINT32_C(0xa)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX UINT32_C(0x1)
#define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
#define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
#define HWRM_CFA_EEM_CFG UINT32_C(0x121)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
#define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_CFA_TFLIB UINT32_C(0x125)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
#define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK UINT32_C(0xff0000)
#define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
#define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
#define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED UINT32_C(0x1)
#define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
#define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
#define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE UINT32_C(0x1)
#define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE UINT32_C(0x8)
#define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
#define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE UINT32_C(0x10)
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE UINT32_C(0x20)
#define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK UINT32_C(0xffc0)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK UINT32_C(0x3)
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0x1c)
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0x1fffe0)
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK UINT32_C(0xffc0)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION UINT32_C(0x35)
#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK UINT32_C(0x3)
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK UINT32_C(0x3fc)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0x3fffc00)
#define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED UINT32_C(0x36)
#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK UINT32_C(0x7fffffff)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION UINT32_C(0x80000000)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (UINT32_C(0x0) << 31)
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (UINT32_C(0x1) << 31)
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ UINT32_C(0x38)
#define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE UINT32_C(0x39)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE UINT32_C(0x3a)
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE UINT32_C(0x3b)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK UINT32_C(0x3fffffff)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION UINT32_C(0x40000000)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX (UINT32_C(0x0) << 30)
#define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX (UINT32_C(0x1) << 30)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK UINT32_C(0x3fffffff)
#define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION UINT32_C(0x40000000)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX (UINT32_C(0x0) << 30)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX (UINT32_C(0x1) << 30)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE UINT32_C(0x80000000)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 (UINT32_C(0x0) << 31)
#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
#define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 (UINT32_C(0x1) << 31)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE UINT32_C(0x3c)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE UINT32_C(0x2)
#define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE UINT32_C(0x3f)
#define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK UINT32_C(0xff00)
#define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK UINT32_C(0xff0000)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ UINT32_C(0x10000)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 UINT32_C(0x20000)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 UINT32_C(0x40000)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 UINT32_C(0x80000)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP UINT32_C(0x1)
#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE UINT32_C(0x40)
#define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE UINT32_C(0x41)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 UINT32_C(0x10)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 UINT32_C(0x20)
#define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 UINT32_C(0x40)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 UINT32_C(0x80)
#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff00)
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST UINT32_C(0x42)
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE UINT32_C(0x43)
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK UINT32_C(0xffff0000)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK UINT32_C(0xf)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK UINT32_C(0xffff0)
#define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP UINT32_C(0x44)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK UINT32_C(0xe)
#define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK UINT32_C(0xffff0)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK UINT32_C(0xffffffff)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
#define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE UINT32_C(0x47)
#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE UINT32_C(0x48)
#define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
#define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK UINT32_C(0xf)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR UINT32_C(0x4a)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC UINT32_C(0x0)
#define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK UINT32_C(0xfffe)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK UINT32_C(0xffff0000)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6)
#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK UINT32_C(0xffffffff)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_ID_REPRESENTOR_PAIR_CHANGE UINT32_C(0x4e)
#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_CREATED UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_DELETED UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MODIFY (UINT32_C(0x0) << 8)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_IGNORE (UINT32_C(0x1) << 8)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_EP_FID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_REP_FID_MASK UINT32_C(0xffff0000)
#define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
#define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xffffffff)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE UINT32_C(0x3)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
#define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE UINT32_C(0x7)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE UINT32_C(0x9)
#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE UINT32_C(0xa)
#define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae)
#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_EVENT_ID_PEER_MMAP_CHANGE UINT32_C(0x4d)
#define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af)
#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG UINT32_C(0xfe)
#define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK UINT32_C(0xff0000)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK UINT32_C(0xff000000)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY (UINT32_C(0x0) << 1)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY (UINT32_C(0x1) << 1)
#define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK UINT32_C(0xff0000)
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK UINT32_C(0xff000000)
#define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD UINT32_C(0x1c2)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE UINT32_C(0x1c3)
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK UINT32_C(0xfe)
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY UINT32_C(0x1c4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM UINT32_C(0x3)
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6)
#define HWRM_SELFTEST_EXEC UINT32_C(0x201)
#define HWRM_SELFTEST_IRQ UINT32_C(0x202)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK UINT32_C(0xff)
#define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_MFG_OTP_CFG UINT32_C(0x207)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK UINT32_C(0x3f)
#define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK UINT32_C(0xffffffff)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR UINT32_C(0x3)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (UINT32_C(0x1) << 8)
#define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (UINT32_C(0x2) << 8)
#define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK UINT32_C(0xffffff00)
#define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK UINT32_C(0xff)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK UINT32_C(0xff00)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK UINT32_C(0x700)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (UINT32_C(0x0) << 8)
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (UINT32_C(0x1) << 8)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (UINT32_C(0x2) << 8)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (UINT32_C(0x3) << 8)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR UINT32_C(0x800)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (UINT32_C(0x0) << 11)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (UINT32_C(0x1) << 11)
#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_ID_VF_STAT_CHANGE UINT32_C(0x4f)
#define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_VF_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_ACTION_SEQUENCE_ID_MASK UINT32_C(0xffff0000)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA1_STAT_CTX_ID_MASK UINT32_C(0xffffffff)
#define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_EVENT_ID_HOST_COREDUMP UINT32_C(0x50)
#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_OPAQUE_MASK UINT32_C(0xfe)
#define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
#define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
#define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
#define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3)
#define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f)
#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
#define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
#define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
#define TLS_METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
#define TLS_METADATA_BASE_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
#define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
#define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC (UINT32_C(0x1) << 10)
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC (UINT32_C(0x2) << 10)
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS (UINT32_C(0x1) << 12)
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE (UINT32_C(0x2) << 12)
#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
#define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
#define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << 16)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
#define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)
#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << 16)
#define TLS_METADATA_BASE_MSG_KID_LO_MASK UINT32_C(0xfe000000)
#define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK UINT32_C(0x1f)
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
#define TLS_METADATA_INSYNC_MSG_LINK_MASK UINT32_C(0x1e0)
#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
#define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
#define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219)
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC (UINT32_C(0x1) << 10)
#define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a)
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC (UINT32_C(0x2) << 10)
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS (UINT32_C(0x1) << 12)
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE (UINT32_C(0x2) << 12)
#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
#define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
#define HWRM_PORT_POE_CFG UINT32_C(0x230)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << 16)
#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK UINT32_C(0xfe000000)
#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
#define HWRM_PORT_POE_QCFG UINT32_C(0x231)
#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK UINT32_C(0x1f)
#define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
#define TLS_METADATA_RESYNC_MSG_LINK_MASK UINT32_C(0x1e0)
#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
#define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
#define HWRM_UDCC_QCAPS UINT32_C(0x258)
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
#define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
#define HWRM_UDCC_CFG UINT32_C(0x259)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << 16)
#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK UINT32_C(0xfe000000)
#define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
#define HWRM_UDCC_QCFG UINT32_C(0x25a)
#define TX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
#define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b)
#define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
#define TX_DOORBELL_KEY_TX (UINT32_C(0x0) << 28)
#define RX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
#define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c)
#define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
#define RX_DOORBELL_KEY_RX (UINT32_C(0x1) << 28)
#define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d)
#define CMPL_DOORBELL_IDX_MASK UINT32_C(0xffffff)
#define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000)
#define CMPL_DOORBELL_MASK UINT32_C(0x8000000)
#define HWRM_UDCC_COMP_CFG UINT32_C(0x25e)
#define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
#define CMPL_DOORBELL_KEY_CMPL (UINT32_C(0x2) << 28)
#define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f)
#define STATUS_DOORBELL_IDX_MASK UINT32_C(0xffffff)
#define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
#define STATUS_DOORBELL_KEY_STAT (UINT32_C(0x3) << 28)
#define HWRM_UDCC_COMP_QUERY UINT32_C(0x260)
#define PUSH32_DOORBELL_IDX_MASK UINT32_C(0xffffff)
#define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000)
#define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
#define PUSH32_DOORBELL_KEY_PUSH (UINT32_C(0x4) << 28)
#define PUSH32_DOORBELL_TYPE_MASK UINT32_C(0x3f)
#define PUSH32_DOORBELL_TYPE_TX_BD_LONG UINT32_C(0x10)
#define PUSH32_DOORBELL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x261)
#define PUSH32_DOORBELL_FLAGS_PACKET_END UINT32_C(0x40)
#define PUSH32_DOORBELL_FLAGS_NO_CMPL UINT32_C(0x80)
#define PUSH32_DOORBELL_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
#define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x262)
#define PUSH32_DOORBELL_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define PUSH32_DOORBELL_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
#define PUSH32_DOORBELL_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
#define PUSH32_DOORBELL_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
#define PUSH32_DOORBELL_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
#define PUSH32_DOORBELL_FLAGS_COAL_NOW UINT32_C(0x8000)
#define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x263)
#define PUSH32_DOORBELL_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define HWRM_TF UINT32_C(0x2bc)
#define PUSH32_DOORBELL_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4)
#define PUSH32_DOORBELL_LFLAGS_STAMP UINT32_C(0x8)
#define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
#define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
#define PUSH32_DOORBELL_LFLAGS_LSO UINT32_C(0x20)
#define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40)
#define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
#define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80)
#define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
#define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define PUSH32_DOORBELL_HDR_SIZE_MASK UINT32_C(0x1ff)
#define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
#define PUSH32_DOORBELL_MSS_MASK UINT32_C(0x7fff)
#define PUSH32_DOORBELL_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
#define PUSH32_DOORBELL_CFA_META_VLAN_DE UINT32_C(0x1000)
#define PUSH32_DOORBELL_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
#define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define PUSH32_DOORBELL_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define PUSH32_DOORBELL_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
#define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
#define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
#define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL UINT32_C(0x0)
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME UINT32_C(0x1)
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2)
#define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF UINT32_C(0x3)
#define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)
#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
#define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
#define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
#define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
#define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
#define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
#define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
#define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
#define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
#define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
#define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
#define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
#define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
#define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8)
#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x10)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x20)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80)
#define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x200)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x800)
#define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS UINT32_C(0x1000)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS UINT32_C(0x2000)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS UINT32_C(0x4000)
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS UINT32_C(0x8000)
#define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302)
#define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303)
#define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x1)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x2)
#define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x4)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x8)
#define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x10)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST UINT32_C(0x20)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST UINT32_C(0x40)
#define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST UINT32_C(0x80)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE UINT32_C(0x100)
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE UINT32_C(0x200)
#define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)
#define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)
#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)
#define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)
#define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)
#define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)
#define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING UINT32_C(0x2)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
#define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED UINT32_C(0x8)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)
#define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED UINT32_C(0x80)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED UINT32_C(0x100)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED UINT32_C(0x200)
#define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED UINT32_C(0x400)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED UINT32_C(0x800)
#define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED UINT32_C(0x1000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED UINT32_C(0x2000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED UINT32_C(0x4000)
#define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED UINT32_C(0x8000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED UINT32_C(0x10000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED UINT32_C(0x20000)
#define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED UINT32_C(0x40000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED UINT32_C(0x80000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE UINT32_C(0x100000)
#define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC UINT32_C(0x200000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE UINT32_C(0x400000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE UINT32_C(0x800000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED UINT32_C(0x1000000)
#define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD UINT32_C(0x2000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED UINT32_C(0x4000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED UINT32_C(0x8000000)
#define HWRM_TFC_TCAM_SET UINT32_C(0x393)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED UINT32_C(0x10000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED UINT32_C(0x20000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED UINT32_C(0x40000000)
#define HWRM_TFC_TCAM_GET UINT32_C(0x394)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED UINT32_C(0x80000000)
#define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)
#define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)
#define HWRM_TFC_TCAM_FREE UINT32_C(0x397)
#define HWRM_TFC_IF_TBL_SET UINT32_C(0x398)
#define HWRM_TFC_IF_TBL_GET UINT32_C(0x399)
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED UINT32_C(0x1)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED UINT32_C(0x2)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED UINT32_C(0x4)
#define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT UINT32_C(0x8)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT UINT32_C(0x10)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT UINT32_C(0x20)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED UINT32_C(0x40)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED UINT32_C(0x80)
#define HWRM_SV UINT32_C(0x400)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED UINT32_C(0x100)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED UINT32_C(0x200)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED UINT32_C(0x400)
#define HWRM_DBG_SERDES_TEST UINT32_C(0xff0e)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE UINT32_C(0x800)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE UINT32_C(0x1000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED UINT32_C(0x2000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED UINT32_C(0x4000)
#define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED UINT32_C(0x8000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED UINT32_C(0x10000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED UINT32_C(0x20000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED UINT32_C(0x40000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED UINT32_C(0x80000)
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED UINT32_C(0x100000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED UINT32_C(0x200000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED UINT32_C(0x400000)
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL UINT32_C(0x800000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED UINT32_C(0x1000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP UINT32_C(0x2000000)
#define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED UINT32_C(0x4000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED UINT32_C(0x8000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED UINT32_C(0x10000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED UINT32_C(0x20000000)
#define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED UINT32_C(0x40000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED UINT32_C(0x80000000)
#define HWRM_DBG_DUMP UINT32_C(0xff14)
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
#define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED UINT32_C(0x1)
#define HWRM_DBG_CFG UINT32_C(0xff16)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED UINT32_C(0x2)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED UINT32_C(0x4)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED UINT32_C(0x8)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED UINT32_C(0x10)
#define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED UINT32_C(0x20)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED UINT32_C(0x40)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED UINT32_C(0x80)
#define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED UINT32_C(0x100)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED UINT32_C(0x200)
#define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED UINT32_C(0x400)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000)
#define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000)
#define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED UINT32_C(0x8000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED UINT32_C(0x10000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED UINT32_C(0x20000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED UINT32_C(0x40000)
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED UINT32_C(0x80000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED UINT32_C(0x100000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED UINT32_C(0x200000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED UINT32_C(0x400000)
#define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED UINT32_C(0x800000)
#define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x1000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED UINT32_C(0x2000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x4000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED UINT32_C(0x8000000)
#define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_PEER_MMAP_SUPPORTED UINT32_C(0x10000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED UINT32_C(0x20000000)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED UINT32_C(0x40000000)
#define HWRM_DBG_QCAPS UINT32_C(0xff20)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED UINT32_C(0x80000000)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN UINT32_C(0x1)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE UINT32_C(0x2)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE UINT32_C(0x4)
#define HWRM_DBG_QCFG UINT32_C(0xff21)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE UINT32_C(0x8)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE UINT32_C(0x10)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP UINT32_C(0x20)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS UINT32_C(0x40)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE UINT32_C(0x80)
#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK UINT32_C(0x1)
#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK UINT32_C(0x2)
#define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
#define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
#define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
#define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP UINT32_C(0x1)
#define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
#define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
#define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
#define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
#define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED UINT32_C(0x4)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED UINT32_C(0x8)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED UINT32_C(0x10)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST UINT32_C(0x20)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF UINT32_C(0x40)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED UINT32_C(0x80)
#define HWRM_DBG_COREDUMP_CAPTURE UINT32_C(0xff2c)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS UINT32_C(0x100)
#define HWRM_DBG_PTRACE UINT32_C(0xff2d)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED UINT32_C(0x200)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED UINT32_C(0x400)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED UINT32_C(0x800)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED UINT32_C(0x1000)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT UINT32_C(0x2000)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV UINT32_C(0x4000)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID UINT32_C(0x8000)
#define HWRM_DBG_SIM_CABLE_STATE UINT32_C(0xff2e)
#define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea)
#define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb)
#define HWRM_NVM_DEFRAG UINT32_C(0xffec)
#define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
#define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define TLV_FLAGS_MORE UINT32_C(0x1)
#define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_NVM_MODIFY UINT32_C(0xfff4)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
#define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK UINT32_C(0x3)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 UINT32_C(0x1)
#define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK UINT32_C(0xc)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2)
#define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2)
#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK UINT32_C(0xf0)
#define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
#define HWRM_NVM_READ UINT32_C(0xfffd)
#define HWRM_NVM_WRITE UINT32_C(0xfffe)
#define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED UINT32_C(0x2)
#define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED UINT32_C(0x4)
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED UINT32_C(0x8)
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED UINT32_C(0x10)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
#define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS2_SRIOV_DSCP_INSERT_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
#define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1)
#define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2)
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE UINT32_C(0x1)
#define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK UINT32_C(0x1fc)
#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE UINT32_C(0x200)
#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE UINT32_C(0x400)
#define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800)
#define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x2000)
#define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
#define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x4000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x8000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x10000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x20000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST UINT32_C(0x40000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST UINT32_C(0x80000)
#define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST UINT32_C(0x100000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE UINT32_C(0x200000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC UINT32_C(0x400000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST UINT32_C(0x800000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE UINT32_C(0x1000000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS UINT32_C(0x2000000)
#define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
#define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS UINT32_C(0x4000000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE UINT32_C(0x8000000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE UINT32_C(0x20000000)
#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE UINT32_C(0x40000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_ENABLES_MRU UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x4)
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x8)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x10)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x20)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x40)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x80)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x100)
#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x200)
#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN UINT32_C(0x400)
#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR UINT32_C(0x800)
#define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW UINT32_C(0x1000)
#define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
#define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW UINT32_C(0x2000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE UINT32_C(0x8000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS UINT32_C(0x10000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE UINT32_C(0x20000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS UINT32_C(0x40000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x80000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE UINT32_C(0x100000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX UINT32_C(0x200000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE UINT32_C(0x400000)
#define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT UINT32_C(0x800000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS UINT32_C(0x2000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW UINT32_C(0x4000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW UINT32_C(0x8000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_TPID UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU UINT32_C(0x20000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS UINT32_C(0x40000000)
#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS UINT32_C(0x80000000)
#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
#define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK UINT32_C(0x0)
#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN UINT32_C(0x3)
#define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
#define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
#define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK UINT32_C(0x3)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 UINT32_C(0x0)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK UINT32_C(0xc)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2)
#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xf0)
#define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
#define TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE UINT32_C(0x10)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE UINT32_C(0x20)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE UINT32_C(0x40)
#define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE UINT32_C(0x80)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE UINT32_C(0x100)
#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE UINT32_C(0x200)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST UINT32_C(0x2)
#define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS UINT32_C(0x4)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS UINT32_C(0x8)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF UINT32_C(0x10)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF UINT32_C(0x20)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF UINT32_C(0x40)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF UINT32_C(0x80)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF UINT32_C(0x100)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF UINT32_C(0x200)
#define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG UINT32_C(0x400)
#define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
#define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1)
#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2)
#define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE UINT32_C(0x1)
#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX UINT32_C(0x2)
#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED UINT32_C(0x3)
#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT UINT32_C(0x4)
#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
#define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
#define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4)
#define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE UINT32_C(0x8)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT UINT32_C(0x10)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT UINT32_C(0x20)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT UINT32_C(0x40)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT UINT32_C(0x80)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT UINT32_C(0x100)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT UINT32_C(0x200)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT UINT32_C(0x400)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE UINT32_C(0x800)
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_EGRESS_NIC_FLOW_MODE UINT32_C(0x1000)
#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
#define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED UINT32_C(0x1)
#define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN UINT32_C(0x1)
#define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
#define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
#define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
#define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2 UINT32_C(0x0)
#define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL UINT32_C(0x0)
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL UINT32_C(0x1)
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC UINT32_C(0x2)
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1)
#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT UINT32_C(0x10)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC UINT32_C(0x40)
#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC UINT32_C(0x80)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK UINT32_C(0xf)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 UINT32_C(0x40)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 UINT32_C(0x80)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 UINT32_C(0x100)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 UINT32_C(0x200)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 UINT32_C(0x400)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 UINT32_C(0x800)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 UINT32_C(0x1000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 UINT32_C(0x2000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM UINT32_C(0x8000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 UINT32_C(0x10000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 UINT32_C(0x20000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 UINT32_C(0x40000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC UINT32_C(0x80000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC UINT32_C(0x100000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 UINT32_C(0x40)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 UINT32_C(0x80)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 UINT32_C(0x100)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 UINT32_C(0x200)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 UINT32_C(0x400)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 UINT32_C(0x800)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 UINT32_C(0x1000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 UINT32_C(0x2000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM UINT32_C(0x8000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 UINT32_C(0x10000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 UINT32_C(0x20000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 UINT32_C(0x40000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC UINT32_C(0x80000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC UINT32_C(0x100000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK UINT32_C(0xf)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED UINT32_C(0x10)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED UINT32_C(0x40)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED UINT32_C(0x80)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED UINT32_C(0x100)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED UINT32_C(0x200)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED UINT32_C(0x400)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED UINT32_C(0x800)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED UINT32_C(0x1000)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED UINT32_C(0x2000)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED UINT32_C(0x4000)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE UINT32_C(0x8000)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED UINT32_C(0x8)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE UINT32_C(0x8)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE UINT32_C(0x10)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE UINT32_C(0x20)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE UINT32_C(0x40)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE UINT32_C(0x80)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT UINT32_C(0x1)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE UINT32_C(0x2)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE UINT32_C(0x4)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD UINT32_C(0x8)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP UINT32_C(0x10)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE UINT32_C(0x20)
#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME UINT32_C(0x40)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL UINT32_C(0x1)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL UINT32_C(0x2)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 UINT32_C(0x1)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 UINT32_C(0x2)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 UINT32_C(0x3)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 UINT32_C(0x4)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 UINT32_C(0x5)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 UINT32_C(0x6)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 UINT32_C(0x7)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID UINT32_C(0xff)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE UINT32_C(0x0)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K UINT32_C(0x1)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K UINT32_C(0x2)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M UINT32_C(0x3)
#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M UINT32_C(0x4)
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID UINT32_C(0x1)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID UINT32_C(0x2)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE UINT32_C(0x4)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER UINT32_C(0x8)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
#define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE UINT32_C(0x4)
#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
#define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS UINT32_C(0x1)
#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA0_TRACE UINT32_C(0x26)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA1_TRACE UINT32_C(0x27)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA2_TRACE UINT32_C(0x28)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP1_TRACE UINT32_C(0x29)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_ENABLES_NEXT_BS_OFFSET UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE UINT32_C(0x1d)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA0_TRACE UINT32_C(0x26)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA1_TRACE UINT32_C(0x27)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA2_TRACE UINT32_C(0x28)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP1_TRACE UINT32_C(0x29)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA0_TRACE UINT32_C(0x26)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA1_TRACE UINT32_C(0x27)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA2_TRACE UINT32_C(0x28)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP1_TRACE UINT32_C(0x29)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA0_TRACE UINT32_C(0x26)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA1_TRACE UINT32_C(0x27)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA2_TRACE UINT32_C(0x28)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP1_TRACE UINT32_C(0x29)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP UINT32_C(0x0)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA0_TRACE UINT32_C(0x26)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA1_TRACE UINT32_C(0x27)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA2_TRACE UINT32_C(0x28)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP1_TRACE UINT32_C(0x29)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_FW_DBG_TRACE UINT32_C(0x10)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_FW_BIN_DBG_TRACE UINT32_C(0x20)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_NEXT_BS_OFFSET UINT32_C(0x40)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT UINT32_C(0x1)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT UINT32_C(0x2)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT UINT32_C(0x4)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT UINT32_C(0x8)
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK UINT32_C(0xf0)
#define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE UINT32_C(0x2)
#define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID UINT32_C(0x2)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK UINT32_C(0x3)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC UINT32_C(0x1)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK UINT32_C(0xfffffffc)
#define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK UINT32_C(0xffffff)
#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE UINT32_C(0x1)
#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK UINT32_C(0x2)
#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK UINT32_C(0x4)
#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE UINT32_C(0x1)
#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE UINT32_C(0x1)
#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED UINT32_C(0x2)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1)
#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2)
#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4)
#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8)
#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS UINT32_C(0x1)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x4)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE UINT32_C(0x8)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID UINT32_C(0x10)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xe0)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK UINT32_C(0xfc)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK UINT32_C(0xfe)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 (UINT32_C(0x0) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 (UINT32_C(0x1) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 (UINT32_C(0x2) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 (UINT32_C(0x3) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 (UINT32_C(0x4) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 (UINT32_C(0x5) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 (UINT32_C(0x6) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 (UINT32_C(0x7) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 (UINT32_C(0x8) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 (UINT32_C(0x9) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 (UINT32_C(0xa) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 (UINT32_C(0xb) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 (UINT32_C(0xc) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 (UINT32_C(0xd) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 (UINT32_C(0xe) << 12)
#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 (UINT32_C(0xf) << 12)
#define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 (UINT32_C(0x0) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 (UINT32_C(0x1) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 (UINT32_C(0x2) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 (UINT32_C(0x3) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 (UINT32_C(0x4) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 (UINT32_C(0x5) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 (UINT32_C(0x6) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 (UINT32_C(0x7) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 (UINT32_C(0x8) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 (UINT32_C(0x9) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 (UINT32_C(0xa) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 (UINT32_C(0xb) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 (UINT32_C(0xc) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 (UINT32_C(0xd) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 (UINT32_C(0xe) << 12)
#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 (UINT32_C(0xf) << 12)
#define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE UINT32_C(0x1)
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE UINT32_C(0x2)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE UINT32_C(0x4)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 UINT32_C(0x1)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 UINT32_C(0x2)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 UINT32_C(0x4)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 UINT32_C(0x8)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 UINT32_C(0x10)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 UINT32_C(0x20)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 UINT32_C(0x40)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 UINT32_C(0x80)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 UINT32_C(0x100)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 UINT32_C(0x200)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 UINT32_C(0x400)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 UINT32_C(0x800)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 UINT32_C(0x1000)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 UINT32_C(0x2000)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 UINT32_C(0x4000)
#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 UINT32_C(0x8000)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE UINT32_C(0x1)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS UINT32_C(0x2)
#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE UINT32_C(0x4)
#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR UINT32_C(0x8)
#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR UINT32_C(0x10)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE UINT32_C(0x40)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE UINT32_C(0x800)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE UINT32_C(0x1000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN UINT32_C(0x4000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE UINT32_C(0x8000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE UINT32_C(0x10000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE UINT32_C(0x20000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE UINT32_C(0x40000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE UINT32_C(0x80000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE UINT32_C(0x100000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE UINT32_C(0x200000)
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE UINT32_C(0x400000)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK UINT32_C(0x200)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED UINT32_C(0x800)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK UINT32_C(0x1000)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2 UINT32_C(0x2000)
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK UINT32_C(0x4000)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_LINK_RELEASE UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_MGMT_VALID UINT32_C(0x80)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB UINT32_C(0x4)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB UINT32_C(0x8)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB UINT32_C(0x10)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB UINT32_C(0x20)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 UINT32_C(0x40)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 UINT32_C(0x80)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 UINT32_C(0x100)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 UINT32_C(0x200)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 UINT32_C(0x400)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 UINT32_C(0x800)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 UINT32_C(0x1000)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 UINT32_C(0x2000)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT UINT32_C(0x6)
#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK UINT32_C(0xf)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 UINT32_C(0x1)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK UINT32_C(0xf0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE (UINT32_C(0x0) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (UINT32_C(0x1) << 4)
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (UINT32_C(0x2) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (UINT32_C(0x3) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (UINT32_C(0x4) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (UINT32_C(0x5) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (UINT32_C(0x6) << 4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_800GB UINT32_C(0x1f40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB UINT32_C(0x80)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
#define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
#define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
#define CE_BDS_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT UINT32_C(0x5)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_OVERHEATED UINT32_C(0x6)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 UINT32_C(0x5)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX UINT32_C(0x6)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR UINT32_C(0x7)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L UINT32_C(0xb)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S UINT32_C(0xc)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N UINT32_C(0xd)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR UINT32_C(0xe)
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 UINT32_C(0xf)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 UINT32_C(0x11)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 UINT32_C(0x12)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 UINT32_C(0x13)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 UINT32_C(0x14)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 UINT32_C(0x15)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 UINT32_C(0x16)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 UINT32_C(0x17)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE UINT32_C(0x18)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET UINT32_C(0x19)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX UINT32_C(0x1a)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX UINT32_C(0x1b)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 UINT32_C(0x1c)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 UINT32_C(0x1d)
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 UINT32_C(0x1000000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 UINT32_C(0x1e)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR UINT32_C(0x21)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR UINT32_C(0x22)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER UINT32_C(0x23)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 UINT32_C(0x24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 UINT32_C(0x25)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 UINT32_C(0x26)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 UINT32_C(0x27)
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 UINT32_C(0x2000000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR UINT32_C(0x28)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR UINT32_C(0x29)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR UINT32_C(0x2a)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER UINT32_C(0x2b)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2 UINT32_C(0x2c)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2 UINT32_C(0x2d)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2 UINT32_C(0x2e)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2 UINT32_C(0x2f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8 UINT32_C(0x30)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8 UINT32_C(0x31)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8 UINT32_C(0x32)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8 UINT32_C(0x33)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4 UINT32_C(0x34)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4 UINT32_C(0x35)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4 UINT32_C(0x36)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4 UINT32_C(0x37)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASECR8 UINT32_C(0x38)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASESR8 UINT32_C(0x39)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASELR8 UINT32_C(0x3a)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEER8 UINT32_C(0x3b)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEFR8 UINT32_C(0x3c)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 UINT32_C(0x3d)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
#define CE_BDS_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20)
#define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE UINT32_C(0x40)
#define CE_BDS_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI UINT32_C(0x80)
#define CE_BDS_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB UINT32_C(0x80)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB UINT32_C(0x2000)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX UINT32_C(0x1)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK UINT32_C(0xff000000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN (UINT32_C(0x0) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP (UINT32_C(0x3) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD (UINT32_C(0x18) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 (UINT32_C(0x1e) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD (UINT32_C(0x1f) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP (UINT32_C(0x20) << 24)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2)
#define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED UINT32_C(0x80)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED UINT32_C(0x4000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB UINT32_C(0x4)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x2)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE UINT32_C(0x20)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x40)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE UINT32_C(0x80)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x100)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE UINT32_C(0x400)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE UINT32_C(0x800)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE UINT32_C(0x1000)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS UINT32_C(0x2000)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE UINT32_C(0x4000)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE UINT32_C(0x8000)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI UINT32_C(0x4)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI UINT32_C(0x10)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG UINT32_C(0x100)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB UINT32_C(0x200)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE UINT32_C(0x400)
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_LOAD_CONTROL UINT32_C(0x800)
#define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
#define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 UINT32_C(0x1)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
#define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0)
#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
#define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000)
#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24)
#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x2)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x4)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x8)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x20)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD UINT32_C(0x1)
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK UINT32_C(0x7fff)
#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID UINT32_C(0x8000)
#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0)
#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS UINT32_C(0x1)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS UINT32_C(0x4)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS UINT32_C(0x8)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK UINT32_C(0x10)
#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED UINT32_C(0x20)
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_64B_PHC_TIME UINT32_C(0x40)
#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK (UINT32_C(0x0) << 24)
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK UINT32_C(0xfffff0)
#define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK (UINT32_C(0x1) << 24)
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR UINT32_C(0x1)
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN UINT32_C(0x2)
#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED UINT32_C(0x1)
#define HWRM_PORT_LPBK_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME UINT32_C(0x2)
#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_TS_REQ_TIMEOUT UINT32_C(0x1)
#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_SEQ_ID UINT32_C(0x2)
#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_HDR_OFFSET UINT32_C(0x4)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 (UINT32_C(0x1) << 24)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 (UINT32_C(0x2) << 24)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 (UINT32_C(0x3) << 24)
#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED UINT32_C(0x2)
#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET UINT32_C(0x10)
#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 (UINT32_C(0x2) << 28)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN UINT32_C(0x40)
#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE (UINT32_C(0x3) << 28)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS UINT32_C(0x80)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc)
#define CE_BDS_QUIC_ADD_DATA_MSG__QUIC (UINT32_C(0x4) << 28)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB UINT32_C(0x80)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB UINT32_C(0x400)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB UINT32_C(0x40)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB UINT32_C(0x80)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB UINT32_C(0x100)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB UINT32_C(0x200)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB UINT32_C(0x400)
#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB UINT32_C(0x800)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB UINT32_C(0x40)
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK UINT32_C(0xffffff)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK UINT32_C(0xff000000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK UINT32_C(0xffffff)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK UINT32_C(0xff000000)
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 6)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 6)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_REMOTE_LPBK_UNSUPPORTED UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 UINT32_C(0x40)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 UINT32_C(0x80)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 UINT32_C(0x100)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 UINT32_C(0x200)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 UINT32_C(0x400)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 UINT32_C(0x800)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 UINT32_C(0x2000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB UINT32_C(0x1)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB UINT32_C(0x2)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB UINT32_C(0x4)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB UINT32_C(0x8)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB UINT32_C(0x10)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB UINT32_C(0x20)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 UINT32_C(0x40)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 UINT32_C(0x80)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 UINT32_C(0x100)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 UINT32_C(0x200)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 UINT32_C(0x400)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 UINT32_C(0x800)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 UINT32_C(0x1000)
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 UINT32_C(0x2000)
#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_BANK_NUMBER UINT32_C(0x2)
#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_BANK_NUMBER UINT32_C(0x2)
#define BD_BASE_TYPE_MASK UINT32_C(0x3f)
#define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
#define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
#define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON UINT32_C(0x8)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF UINT32_C(0x10)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID UINT32_C(0x20)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID UINT32_C(0x40)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE UINT32_C(0x80)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR UINT32_C(0x100)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON UINT32_C(0x200)
#define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF UINT32_C(0x400)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID UINT32_C(0x800)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID UINT32_C(0x1000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE UINT32_C(0x2000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR UINT32_C(0x4000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON UINT32_C(0x8000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF UINT32_C(0x10000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID UINT32_C(0x20000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID UINT32_C(0x40000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE UINT32_C(0x80000)
#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR UINT32_C(0x100000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON UINT32_C(0x200000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF UINT32_C(0x400000)
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID UINT32_C(0x800000)
#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
#define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
#define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
#define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
#define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
#define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
#define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
#define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
#define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
#define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
#define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
#define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD UINT32_C(0x1)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
#define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
#define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP UINT32_C(0x1)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID UINT32_C(0x2)
#define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID UINT32_C(0x4)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 UINT32_C(0x8)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 UINT32_C(0x10)
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_T_CODE UINT32_C(0x20)
#define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
#define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)
#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1)
#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE UINT32_C(0x0)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE UINT32_C(0x1)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT UINT32_C(0x2)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE UINT32_C(0x3)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE UINT32_C(0x4)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE UINT32_C(0x5)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE UINT32_C(0x6)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE UINT32_C(0x7)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG UINT32_C(0x8)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT UINT32_C(0x9)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ UINT32_C(0xa)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE UINT32_C(0xb)
#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP UINT32_C(0xc)
#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE UINT32_C(0x1)
#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_BIG_BUFFER UINT32_C(0x2)
#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE UINT32_C(0x4)
#define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
#define HWRM_PORT_DSC_DUMP_OUTPUT_FLAGS_BIG_BUFFER UINT32_C(0x1)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 UINT32_C(0x1)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 UINT32_C(0x2)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS UINT32_C(0x4)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL UINT32_C(0x8)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L UINT32_C(0x10)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE UINT32_C(0x20)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS UINT32_C(0x40)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 UINT32_C(0x1)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 UINT32_C(0x2)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS UINT32_C(0x4)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL UINT32_C(0x8)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L UINT32_C(0x10)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE UINT32_C(0x20)
#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS UINT32_C(0x40)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS UINT32_C(0x1)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS UINT32_C(0x2)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 UINT32_C(0x4)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 UINT32_C(0x8)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS UINT32_C(0x10)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT UINT32_C(0x20)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL UINT32_C(0x40)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L UINT32_C(0x80)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE UINT32_C(0x100)
#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS UINT32_C(0x200)
#define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4_112G UINT32_C(0x5)
#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G UINT32_C(0x6)
#define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2)
#define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4_112 UINT32_C(0x5)
#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 UINT32_C(0x6)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
#define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID UINT32_C(0x1)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE UINT32_C(0x2)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE UINT32_C(0x3)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX UINT32_C(0x4)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM UINT32_C(0x5)
#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED UINT32_C(0x6)
#define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
#define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
#define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
#define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1)
#define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
#define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1)
#define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1)
#define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
#define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x1)
#define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_REMOTE_LPBK_SUPPORTED UINT32_C(0x2)
#define HWRM_PORT_POE_CFG_INPUT_FLAGS_ENABLE_POE UINT32_C(0x1)
#define HWRM_PORT_POE_QCFG_OUTPUT_STATUS_POE_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
#define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
#define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED UINT32_C(0x100)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED UINT32_C(0x200)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED UINT32_C(0x400)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED UINT32_C(0x800)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED UINT32_C(0x1000)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED UINT32_C(0x2000)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED UINT32_C(0x4000)
#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED UINT32_C(0x8000)
#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED UINT32_C(0x100)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED UINT32_C(0x200)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED UINT32_C(0x400)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED UINT32_C(0x800)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED UINT32_C(0x1000)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED UINT32_C(0x2000)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED UINT32_C(0x4000)
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED UINT32_C(0x8000)
#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
#define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
#define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID UINT32_C(0x1)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID UINT32_C(0x2)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID UINT32_C(0x4)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID UINT32_C(0x8)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID UINT32_C(0x10)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID UINT32_C(0x20)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID UINT32_C(0x40)
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID UINT32_C(0x80)
#define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
#define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
#define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10)
#define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
#define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI UINT32_C(0x1)
#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI UINT32_C(0x1)
#define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
#define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID UINT32_C(0x1)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID UINT32_C(0x2)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID UINT32_C(0x4)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID UINT32_C(0x8)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID UINT32_C(0x10)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID UINT32_C(0x20)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID UINT32_C(0x40)
#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID UINT32_C(0x80)
#define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
#define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID UINT32_C(0x1)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID UINT32_C(0x2)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID UINT32_C(0x4)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID UINT32_C(0x8)
#define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID UINT32_C(0x10)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID UINT32_C(0x20)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID UINT32_C(0x40)
#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID UINT32_C(0x80)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW UINT32_C(0x10)
#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING UINT32_C(0x1)
#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT UINT32_C(0x0)
#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT UINT32_C(0x1)
#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
#define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
#define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7)
#define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_MODE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
#define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3)
#define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7)
#define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
#define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
#define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
#define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
#define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_MODE_CAP UINT32_C(0x2)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1)
#define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_PCIE_BW_EFF_CAP UINT32_C(0x8)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_XOFF_HEADROOM_FACTOR_CAP UINT32_C(0x10)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x20)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x40)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x80)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x100)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_PIPE_COS_LATENCY_CAP UINT32_C(0x200)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_PIPE_COS_LATENCY_CAP UINT32_C(0x400)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_COS_SHARED_MIN_RATIO_CAP UINT32_C(0x800)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x1000)
#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x2000)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1)
#define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x8)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x10)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x20)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x40)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x80)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_MAX_TBM_CELLS_PRERESERVED_CAP UINT32_C(0x100)
#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x200)
#define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
#define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
#define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_PCIE_BW_EFF UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_XOFF_HEADROOM_FACTOR UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x100)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_PIPE_COS_LATENCY UINT32_C(0x200)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_PIPE_COS_LATENCY UINT32_C(0x400)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_COS_SHARED_MIN_RATIO UINT32_C(0x800)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x1000)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x2000)
#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
#define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x8)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x20)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x40)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x80)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_MAX_TBM_CELLS_PRERESERVED UINT32_C(0x100)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x200)
#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID UINT32_C(0x2)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID UINT32_C(0x1)
#define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID UINT32_C(0x2)
#define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID UINT32_C(0x4)
#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
#define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
#define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40)
#define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x80)
#define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
#define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
#define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
#define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
#define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
#define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID UINT32_C(0x20)
#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID UINT32_C(0x40)
#define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID UINT32_C(0x80)
#define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE UINT32_C(0x100)
#define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE UINT32_C(0x200)
#define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
#define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
#define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
#define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE UINT32_C(0x80)
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x100)
#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
#define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
#define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1)
#define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2)
#define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP UINT32_C(0x40)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP UINT32_C(0x80)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP UINT32_C(0x100)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP UINT32_C(0x200)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP UINT32_C(0x400)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP UINT32_C(0x800)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP UINT32_C(0x1000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP UINT32_C(0x2000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP UINT32_C(0x4000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP UINT32_C(0x8000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP UINT32_C(0x10000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP UINT32_C(0x20000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP UINT32_C(0x40000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP UINT32_C(0x80000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP UINT32_C(0x100000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP UINT32_C(0x200000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP UINT32_C(0x400000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP UINT32_C(0x800000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP UINT32_C(0x1000000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP UINT32_C(0x2000000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x4000000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED UINT32_C(0x8000000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP UINT32_C(0x10000000)
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP UINT32_C(0x20000000)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8)
#define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO UINT32_C(0x100)
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN UINT32_C(0x10)
#define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
#define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800)
#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000)
#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000)
#define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000)
#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400)
#define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1)
#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2)
#define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT UINT32_C(0x4)
#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0)
#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR UINT32_C(0x1)
#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
#define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY UINT32_C(0x1)
#define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80)
#define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR UINT32_C(0x1)
#define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6)
#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
#define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x40)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4)
#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID UINT32_C(0x8)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40)
#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x80)
#define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff)
#define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID UINT32_C(0x40)
#define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID UINT32_C(0x80)
#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID UINT32_C(0x100)
#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID UINT32_C(0x200)
#define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE UINT32_C(0x400)
#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
#define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID UINT32_C(0x800)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
#define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
#define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
#define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING UINT32_C(0x4)
#define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE UINT32_C(0x8)
#define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf)
#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0)
#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00)
#define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
#define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
#define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
#define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1)
#define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2)
#define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4)
#define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x8)
#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE UINT32_C(0x10)
#define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA UINT32_C(0x20)
#define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
#define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1)
#define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2)
#define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX UINT32_C(0x2)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET UINT32_C(0x4)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE UINT32_C(0x8)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR UINT32_C(0x10)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x20)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR UINT32_C(0x40)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT UINT32_C(0x80)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT UINT32_C(0x100)
#define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK UINT32_C(0x3)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2)
#define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2)
#define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4)
#define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR UINT32_C(0x1)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x2)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR UINT32_C(0x4)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN UINT32_C(0x8)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX UINT32_C(0x10)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT UINT32_C(0x20)
#define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK (UINT32_C(0x0) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR (UINT32_C(0x1) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR (UINT32_C(0x2) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR (UINT32_C(0x3) << 6)
#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED UINT32_C(0x1)
#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_RESERVATION_ENABLED UINT32_C(0x2)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR (UINT32_C(0x4) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR (UINT32_C(0x5) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL (UINT32_C(0x6) << 6)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL (UINT32_C(0x7) << 6)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0x30)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE UINT32_C(0x40)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID UINT32_C(0x80)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK UINT32_C(0xff000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ (UINT32_C(0x0) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS UINT32_C(0x20000)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS UINT32_C(0x40000)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE (UINT32_C(0x1) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR (UINT32_C(0x2) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT (UINT32_C(0x3) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE (UINT32_C(0x4) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE (UINT32_C(0x5) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT (UINT32_C(0x6) << 12)
#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK UINT32_C(0xff00000)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0xc)
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf0000000)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 2)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_MASK UINT32_C(0x30)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_NO_UPDATE (UINT32_C(0x0) << 4)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_BYPASS_LKUP (UINT32_C(0x1) << 4)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP (UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_RESTORE_FW_OP (UINT32_C(0x3) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA (UINT32_C(0x2) << 28)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_PROF_FUNC UINT32_C(0x4)
#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_L2_CONTEXT_ID UINT32_C(0x8)
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA (UINT32_C(0x3) << 28)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
#define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80)
#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100)
#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 UINT32_C(0x2)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 UINT32_C(0x4)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST UINT32_C(0x1)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)
#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT UINT32_C(0x1c)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK UINT32_C(0xf0000000)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT UINT32_C(0x14)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK UINT32_C(0xff00000)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT UINT32_C(0x0)
#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK UINT32_C(0xfffff)
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)
#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE (UINT32_C(0x0) << 12)
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE (UINT32_C(0x1) << 12)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL UINT32_C(0x2)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID UINT32_C(0x8)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY UINT32_C(0x10)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x20)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x40)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000)
#define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX UINT32_C(0x80000)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 UINT32_C(0x3a)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD UINT32_C(0xff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1)
#define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
#define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x4)
#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
#define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
#define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000)
#define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
#define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
#define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
#define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
#define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
#define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16)
#define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17)
#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
#define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
#define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
#define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
#define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
#define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
#define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
#define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
#define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
#define CMPL_BASE_V UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
#define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800)
#define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
#define TX_CMPL_V UINT32_C(0x1)
#define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3)
#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x40)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x80)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI UINT32_C(0x100)
#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN UINT32_C(0x200)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x400)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x800)
#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT UINT32_C(0x1000)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC UINT32_C(0x2000)
#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
#define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD UINT32_C(0x1)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP UINT32_C(0x4)
#define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER UINT32_C(0x8)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x20)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x40)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x80)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP UINT32_C(0x100)
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP UINT32_C(0x200)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
#define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP UINT32_C(0x4)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS UINT32_C(0x6)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT UINT32_C(0x7)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
#define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT UINT32_C(0x2000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX UINT32_C(0x3000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT UINT32_C(0x4000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX UINT32_C(0x9000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX UINT32_C(0xa000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX UINT32_C(0xb000)
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX UINT32_C(0xc000)
#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID UINT32_C(0x1)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL UINT32_C(0x2)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT UINT32_C(0x4)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC UINT32_C(0x8000000)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK UINT32_C(0xc0000000)
#define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT (UINT32_C(0x0) << 30)
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT (UINT32_C(0x1) << 30)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
#define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
#define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
#define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER UINT32_C(0x2)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER UINT32_C(0x4)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL UINT32_C(0x8)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL UINT32_C(0x10)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES UINT32_C(0x20)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID UINT32_C(0x40)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE UINT32_C(0x80)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
#define TX_CMPL_COAL_V UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE (UINT32_C(0x0) << 1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE (UINT32_C(0x1) << 1)
#define TX_CMPL_COAL_ERRORS_MASK UINT32_C(0xfffe)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA UINT32_C(0x0)
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
#define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
#define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
#define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
#define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
#define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
#define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM (UINT32_C(0x0) << 7)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA (UINT32_C(0x1) << 7)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL UINT32_C(0x1)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN UINT32_C(0x2)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE UINT32_C(0x4)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE UINT32_C(0x8)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP UINT32_C(0x10)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE UINT32_C(0x20)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS UINT32_C(0x40)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT UINT32_C(0x80)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE UINT32_C(0x100)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 UINT32_C(0x200)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 UINT32_C(0x400)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL UINT32_C(0x800)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE UINT32_C(0x1000)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 UINT32_C(0x2000)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE UINT32_C(0x4000)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
#define TX_CMPL_PACKET_TIMESTAMP_V UINT32_C(0x1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK UINT32_C(0xfffe)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT UINT32_C(0x1)
#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE UINT32_C(0x0)
#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT UINT32_C(0x1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE UINT32_C(0x1)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE UINT32_C(0x0)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE UINT32_C(0x1)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x2)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 1)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 1)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0xc)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 2)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 2)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 2)
#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR UINT32_C(0x40)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0x6)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 1)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 1)
#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x4)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x8)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8)
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x8)
#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR UINT32_C(0x800)
#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED UINT32_C(0x1)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED UINT32_C(0x2)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED UINT32_C(0x4)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED UINT32_C(0x8)
#define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED UINT32_C(0x10)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED UINT32_C(0x20)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED UINT32_C(0x40)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED UINT32_C(0x80)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED UINT32_C(0x100)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED UINT32_C(0x200)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED UINT32_C(0x400)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED UINT32_C(0x800)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED UINT32_C(0x1000)
#define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED UINT32_C(0x2000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED UINT32_C(0x4000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE UINT32_C(0x8000)
#define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED UINT32_C(0x10000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED UINT32_C(0x20000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED UINT32_C(0x40000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED UINT32_C(0x80000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED UINT32_C(0x100000)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED UINT32_C(0x200000)
#define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP UINT32_C(0x1)
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR UINT32_C(0x2)
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST UINT32_C(0x3)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10)
#define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x200)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID UINT32_C(0x800)
#define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
#define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
#define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
#define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_EFID UINT32_C(0x1)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID UINT32_C(0x2)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID UINT32_C(0x3)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_BC_REM UINT32_C(0x1)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_MC_REM UINT32_C(0x2)
#define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM UINT32_C(0x4)
#define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
#define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
#define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION UINT32_C(0x1)
#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR UINT32_C(0x0)
#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
#define RX_PKT_CMPL_V1 UINT32_C(0x1)
#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN UINT32_C(0x1)
#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH UINT32_C(0x2)
#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 UINT32_C(0x4)
#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN UINT32_C(0x1)
#define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K UINT32_C(0x2)
#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH UINT32_C(0x4)
#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH UINT32_C(0x8)
#define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK UINT32_C(0x3)
#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 UINT32_C(0x2)
#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 UINT32_C(0x3)
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DMA UINT32_C(0x2)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
#define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
#define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_V2 UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM UINT32_C(0x1)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM UINT32_C(0x2)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER UINT32_C(0x4)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER UINT32_C(0x8)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION UINT32_C(0x10)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC UINT32_C(0x40)
#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL UINT32_C(0x80)
#define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM UINT32_C(0x1)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM UINT32_C(0x2)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER UINT32_C(0x4)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER UINT32_C(0x8)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION UINT32_C(0x10)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC UINT32_C(0x40)
#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL UINT32_C(0x80)
#define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
#define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
#define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
#define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
#define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
#define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION (UINT32_C(0x3) << 7)
#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10)
#define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL UINT32_C(0x2)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
#define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED UINT32_C(0x3)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40)
#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0)
#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED UINT32_C(0x2)
#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_DUP_HOST_BUF UINT32_C(0x2)
#define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID UINT32_C(0x1)
#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
#define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT UINT32_C(0x7)
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
#define HWRM_FW_RESET_INPUT_FLAGS_FW_ACTIVATION UINT32_C(0x2)
#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5)
#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6)
#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER UINT32_C(0x3)
#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE UINT32_C(0x0)
#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET UINT32_C(0x1)
#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT UINT32_C(0x2)
#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT UINT32_C(0x3)
#define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE UINT32_C(0x100)
#define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0)
#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
#define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0)
#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b)
#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d)
#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f)
#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421)
#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422)
#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424)
#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426)
#define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP UINT32_C(0x427)
#define HWRM_STRUCT_HDR_STRUCT_ID_PEER_MMAP UINT32_C(0x429)
#define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1)
#define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa)
#define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64)
#define HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF UINT32_C(0xc8)
#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0)
#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1)
#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2)
#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0)
#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1)
#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2)
#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff)
#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2)
#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3)
#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4)
#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8)
#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2)
#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3)
#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_V2 UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0)
#define RX_PKT_V2_CMPL_HI_ERRORS_MASK UINT32_C(0xfffe)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0)
#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5)
#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1)
#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2)
#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED UINT32_C(0x0)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202)
#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK UINT32_C(0x70)
#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 4)
#define HWRM_FW_IPC_MSG_INPUT_ENABLES_COMMAND_ID UINT32_C(0x1)
#define HWRM_FW_IPC_MSG_INPUT_ENABLES_SRC_PROCESSOR UINT32_C(0x2)
#define HWRM_FW_IPC_MSG_INPUT_ENABLES_DATA_OFFSET UINT32_C(0x4)
#define HWRM_FW_IPC_MSG_INPUT_ENABLES_LENGTH UINT32_C(0x8)
#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1)
#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION (UINT32_C(0x1) << 4)
#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION UINT32_C(0x3)
#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_CFW UINT32_C(0x1)
#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_BONO UINT32_C(0x2)
#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_APE UINT32_C(0x3)
#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG UINT32_C(0x4)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN (UINT32_C(0x2) << 4)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR (UINT32_C(0x3) << 4)
#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR (UINT32_C(0x4) << 4)
#define HWRM_FW_ECN_CFG_INPUT_FLAGS_ENABLE_ECN UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL (UINT32_C(0x5) << 4)
#define HWRM_FW_ECN_QCFG_OUTPUT_FLAGS_ENABLE_ECN UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR (UINT32_C(0x6) << 4)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_BOOTED UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR (UINT32_C(0x7) << 4)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_MISMATCH UINT32_C(0x2)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_BOOTED UINT32_C(0x4)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_MISMATCH UINT32_C(0x8)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_BOOTED UINT32_C(0x10)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_MISMATCH UINT32_C(0x20)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SECOND_RT UINT32_C(0x40)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FASTBOOTED UINT32_C(0x80)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_BOOTED UINT32_C(0x100)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_MISMATCH UINT32_C(0x200)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_MBR_CORRUPT UINT32_C(0x400)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CFG_MISMATCH UINT32_C(0x800)
#define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR UINT32_C(0x100)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH UINT32_C(0x1000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_BOOTED UINT32_C(0x2000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_MISMATCH UINT32_C(0x4000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_BOOTED UINT32_C(0x8000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_MISMATCH UINT32_C(0x10000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT2_BOOTED UINT32_C(0x20000)
#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT2_MISMATCH UINT32_C(0x40000)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_INSTALL UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_ACTIVE UINT32_C(0x2)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define HWRM_FW_LIVEPATCH_INPUT_OPCODE_ACTIVATE UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE UINT32_C(0x2)
#define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
#define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE UINT32_C(0x1)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET UINT32_C(0x2)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED UINT32_C(0x3)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED UINT32_C(0x4)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED UINT32_C(0x5)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL UINT32_C(0x6)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER UINT32_C(0x7)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE UINT32_C(0x8)
#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SBI UINT32_C(0x1)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT UINT32_C(0x2)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT UINT32_C(0x4)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_DIR_HDR UINT32_C(0x8)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_WRITE_MBR UINT32_C(0x10)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CFG UINT32_C(0x20)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU UINT32_C(0x40)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT2 UINT32_C(0x80)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_GXRT UINT32_C(0x100)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT2 UINT32_C(0x200)
#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_ACTION UINT32_C(0x80000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_MASK UINT32_C(0xff)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_IN_PROGRESS UINT32_C(0x1)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_TIMEOUT UINT32_C(0x2)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL UINT32_C(0x3)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_ERR UINT32_C(0x40000000)
#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_COMPLETE UINT32_C(0x80000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x6) << 9)
#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x7) << 9)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define HWRM_FW_STATE_QUIESCE_INPUT_FLAGS_ERROR_RECOVERY UINT32_C(0x1)
#define HWRM_FW_STATE_QUIESCE_OUTPUT_QUIESCE_STATUS_INITIATED UINT32_C(0x80000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define HWRM_FW_STATE_UNQUIESCE_OUTPUT_UNQUIESCE_STATUS_COMPLETE UINT32_C(0x80000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_MASK UINT32_C(0xf)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_MASK UINT32_C(0xff)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR UINT32_C(0x1)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL UINT32_C(0x3)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_RESET_REQUIRED UINT32_C(0x40000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_COMPLETE UINT32_C(0x80000000)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_MASK UINT32_C(0xf)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_1 UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_MASK UINT32_C(0xf0)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_MASK UINT32_C(0xff)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_GENERAL UINT32_C(0x1)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE UINT32_C(0x2)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK UINT32_C(0x3)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED UINT32_C(0x40000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_COMPLETE UINT32_C(0x80000000)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_NVRAM UINT32_C(0x1)
#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_GRC UINT32_C(0x2)
#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART UINT32_C(0x3)
#define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_PERSISTENT UINT32_C(0x1)
#define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_RUNTIME UINT32_C(0x2)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_NONE UINT32_C(0x0)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_PARTIAL UINT32_C(0x1)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_FULL UINT32_C(0x2)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP UINT32_C(0x3)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_EXE UINT32_C(0x1)
#define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_CFG UINT32_C(0x2)
#define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RO UINT32_C(0x0)
#define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW UINT32_C(0x1)
#define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_DISABLE UINT32_C(0x0)
#define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE UINT32_C(0x1)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR (UINT32_C(0x9) << 12)
#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR (UINT32_C(0xa) << 12)
#define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
#define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
#define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_TEMP_NOT_AVAILABLE UINT32_C(0x1)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_PHY_TEMP_NOT_AVAILABLE UINT32_C(0x2)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_NOT_PRESENT UINT32_C(0x4)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_TEMP_NOT_AVAILABLE UINT32_C(0x8)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE UINT32_C(0x10)
#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_THRESHOLD_VALUES_AVAILABLE UINT32_C(0x20)
#define RX_PKT_V3_CMPL_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 UINT32_C(0x17)
#define RX_PKT_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_IN_POWER_AVAILABLE UINT32_C(0x1)
#define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_OUT_POWER_AVAILABLE UINT32_C(0x2)
#define RX_PKT_V3_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define HWRM_REG_POWER_HISTOGRAM_INPUT_FLAGS_CLEAR_HISTOGRAM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT UINT32_C(0x1)
#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_INPUT UINT32_C(0x0)
#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT UINT32_C(0x1)
#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define BUCKET_NO_DATA_FOR_SAMPLE UINT32_C(0x0)
#define BUCKET_RANGE_8W_OR_LESS UINT32_C(0x1)
#define BUCKET_RANGE_8W_TO_9W UINT32_C(0x2)
#define BUCKET_RANGE_9W_TO_10W UINT32_C(0x3)
#define BUCKET_RANGE_10W_TO_11W UINT32_C(0x4)
#define BUCKET_RANGE_11W_TO_12W UINT32_C(0x5)
#define BUCKET_RANGE_12W_TO_13W UINT32_C(0x6)
#define BUCKET_RANGE_13W_TO_14W UINT32_C(0x7)
#define BUCKET_RANGE_14W_TO_15W UINT32_C(0x8)
#define BUCKET_RANGE_15W_TO_16W UINT32_C(0x9)
#define BUCKET_RANGE_16W_TO_18W UINT32_C(0xa)
#define BUCKET_RANGE_18W_TO_20W UINT32_C(0xb)
#define BUCKET_RANGE_20W_TO_22W UINT32_C(0xc)
#define BUCKET_RANGE_22W_TO_24W UINT32_C(0xd)
#define BUCKET_RANGE_24W_TO_26W UINT32_C(0xe)
#define BUCKET_RANGE_26W_TO_28W UINT32_C(0xf)
#define BUCKET_RANGE_28W_TO_30W UINT32_C(0x10)
#define BUCKET_RANGE_30W_TO_32W UINT32_C(0x11)
#define BUCKET_RANGE_32W_TO_34W UINT32_C(0x12)
#define BUCKET_RANGE_34W_TO_36W UINT32_C(0x13)
#define BUCKET_RANGE_36W_TO_38W UINT32_C(0x14)
#define BUCKET_RANGE_38W_TO_40W UINT32_C(0x15)
#define BUCKET_RANGE_40W_TO_42W UINT32_C(0x16)
#define BUCKET_RANGE_42W_TO_44W UINT32_C(0x17)
#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define BUCKET_RANGE_44W_TO_50W UINT32_C(0x18)
#define BUCKET_RANGE_OVER_50W UINT32_C(0x19)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10)
#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION (UINT32_C(0x3) << 7)
#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20)
#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1)
#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff)
#define RX_PKT_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1)
#define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1)
#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0)
#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1)
#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16)
#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17)
#define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16)
#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17)
#define RX_PKT_V3_CMPL_V1 UINT32_C(0x1)
#define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL UINT32_C(0x1)
#define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x2)
#define RX_PKT_V3_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
#define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG UINT32_C(0x1)
#define RX_PKT_V3_CMPL_UNUSED1 UINT32_C(0x40)
#define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2)
#define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE UINT32_C(0x4)
#define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8)
#define HWRM_DBG_CFG_INPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10)
#define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (UINT32_C(0x0) << 7)
#define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_INVALIDATE UINT32_C(0x0)
#define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (UINT32_C(0x1) << 7)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2 (UINT32_C(0x2) << 7)
#define HWRM_DBG_QCAPS_OUTPUT_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM UINT32_C(0x1)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_NVM UINT32_C(0x1)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_HOST_DDR UINT32_C(0x2)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_SOC_DDR UINT32_C(0x4)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_USEQ UINT32_C(0x8)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_COREDUMP_HOST_DDR UINT32_C(0x10)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_COREDUMP_HOST_CAPTURE UINT32_C(0x20)
#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_PTRACE UINT32_C(0x40)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (UINT32_C(0x3) << 7)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (UINT32_C(0x4) << 7)
#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK UINT32_C(0x3)
#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM UINT32_C(0x0)
#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR UINT32_C(0x1)
#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR UINT32_C(0x2)
#define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (UINT32_C(0x5) << 7)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG UINT32_C(0x1)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE UINT32_C(0x4)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10)
#define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (UINT32_C(0x6) << 7)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_TYPE_DDR UINT32_C(0x1)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_MASK UINT32_C(0x3)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_0 UINT32_C(0x0)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_1 UINT32_C(0x1)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 UINT32_C(0x2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_MASK UINT32_C(0x1c)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (UINT32_C(0x7) << 7)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_MASK UINT32_C(0xffe0)
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_NVRAM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (UINT32_C(0x8) << 7)
#define SFLAG_COMPRESSED_ZLIB UINT32_C(0x1)
#define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (UINT32_C(0x9) << 7)
#define HWRM_DBG_COREDUMP_LIST_OUTPUT_FLAGS_MORE UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (UINT32_C(0xa) << 7)
#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_LIVE_DATA UINT32_C(0x1)
#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_CRASH_DATA UINT32_C(0x2)
#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_COLLECT_CTX_L1_CACHE UINT32_C(0x4)
#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK UINT32_C(0xffffff)
#define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS UINT32_C(0x1000000)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (UINT32_C(0xc) << 7)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (UINT32_C(0xd) << 7)
#define HWRM_DBG_COREDUMP_RETRIEVE_OUTPUT_FLAGS_MORE UINT32_C(0x1)
#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (UINT32_C(0xe) << 7)
#define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_10_BIT_ADDRESSING UINT32_C(0x1)
#define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_FAST_MODE UINT32_C(0x2)
#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_READ UINT32_C(0x0)
#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE UINT32_C(0x1)
#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ UINT32_C(0x2)
#define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
#define RX_PKT_V3_CMPL_METADATA1_MASK UINT32_C(0xf000)
#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_TX UINT32_C(0x1)
#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_RX UINT32_C(0x2)
#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ UINT32_C(0x3)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_FATAL UINT32_C(0x0)
#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_ERROR UINT32_C(0x1)
#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_WARNING UINT32_C(0x2)
#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_INFO UINT32_C(0x3)
#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG UINT32_C(0x4)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
#define RX_PKT_V3_CMPL_METADATA1_VALID UINT32_C(0x8000)
#define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define HWRM_DBG_USEQ_FLUSH_INPUT_USEQ_CODE_WORDS UINT32_C(0x1)
#define HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1)
#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA UINT32_C(0x2)
#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END UINT32_C(0x8000)
#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0)
#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE UINT32_C(0x1)
#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE UINT32_C(0x2)
#define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE UINT32_C(0x0)
#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT UINT32_C(0x1)
#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2)
#define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
#define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE UINT32_C(0x0)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE UINT32_C(0x2)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE UINT32_C(0x3)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x4)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x5)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA0_TRACE UINT32_C(0x7)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA1_TRACE UINT32_C(0x8)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA2_TRACE UINT32_C(0x9)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP1_TRACE UINT32_C(0xa)
#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0x7)
#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_EYE_PROJECTION UINT32_C(0x8)
#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_LANE_NO_MASK UINT32_C(0xf)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION UINT32_C(0x10)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION_HORIZONTAL (UINT32_C(0x0) << 4)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION_VERTICAL (UINT32_C(0x1) << 4)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE UINT32_C(0x20)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) << 5)
#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xc0)
#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E8 UINT32_C(0x0)
#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E9 UINT32_C(0x1)
#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2)
#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3)
#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4)
#define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE UINT32_C(0x100)
#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0)
#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_START UINT32_C(0x1)
#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_PROGRESS UINT32_C(0x2)
#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_STOP UINT32_C(0x3)
#define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1)
#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0)
#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1)
#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_RSVD_MASK UINT32_C(0xfe)
#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE UINT32_C(0x400)
#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
#define HWRM_DBG_SIM_CABLE_STATE_INPUT_ACTION_INSERT UINT32_C(0x0)
#define HWRM_DBG_SIM_CABLE_STATE_INPUT_ACTION_REMOVE UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define HWRM_DBG_PTRACE_INPUT_FLAGS_SELECT_IN UINT32_C(0x1)
#define HWRM_DBG_PTRACE_INPUT_FLAGS_SELECT_OUT UINT32_C(0x2)
#define HWRM_DBG_PTRACE_INPUT_FLAGS_GLOBAL_START UINT32_C(0x4)
#define HWRM_DBG_PTRACE_INPUT_FLAGS_GLOBAL_STOP UINT32_C(0x8)
#define HWRM_DBG_PTRACE_OUTPUT_FLAGS_MORE UINT32_C(0x1)
#define HWRM_NVM_RAW_WRITE_BLK_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_V2 UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_ERRORS_MASK UINT32_C(0xfffe)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_NVM_RAW_DUMP_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1)
#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE UINT32_C(0x2)
#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST UINT32_C(0x4)
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR UINT32_C(0x10)
#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR UINT32_C(0x20)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
#define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR UINT32_C(0x100)
#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1)
#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define HWRM_NVM_GET_DEV_INFO_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4)
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY UINT32_C(0x8)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE UINT32_C(0xff)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE UINT32_C(0xfd)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER UINT32_C(0xfb)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER UINT32_C(0xf3)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE UINT32_C(0xf2)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER UINT32_C(0xec)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE UINT32_C(0xeb)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM UINT32_C(0xea)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH UINT32_C(0xe9)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST UINT32_C(0xe8)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER UINT32_C(0xe7)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM UINT32_C(0xe6)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM UINT32_C(0xe5)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH UINT32_C(0xe4)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE UINT32_C(0xe1)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV UINT32_C(0xce)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID UINT32_C(0xcd)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR UINT32_C(0xcc)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID UINT32_C(0xcb)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM UINT32_C(0xc5)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM UINT32_C(0xc4)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM UINT32_C(0xc3)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR UINT32_C(0xb9)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR UINT32_C(0xb8)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR UINT32_C(0xb7)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND UINT32_C(0xb0)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED UINT32_C(0xa7)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK UINT32_C(0x3)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT UINT32_C(0x4)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1)
#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 (UINT32_C(0x2) << 1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (UINT32_C(0x3) << 1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK UINT32_C(0x70)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT UINT32_C(0x80)
#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
#define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
#define RX_PKT_V3_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
#define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CFG_OPTION UINT32_C(0x1)
#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CRASHDUMP UINT32_C(0x2)
#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK UINT32_C(0x0)
#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK UINT32_C(0x1)
#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2)
#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1)
#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2)
#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_STATUS UINT32_C(0x0)
#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_ACQUIRE UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE UINT32_C(0x2)
#define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE UINT32_C(0x100)
#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 8)
#define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3)
#define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc)
#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 8)
#define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1)
#define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2)
#define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3)
#define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4)
#define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5)
#define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6)
#define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8)
#define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9)
#define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa)
#define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc)
#define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
#define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
#define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf)
#define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10)
#define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11)
#define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12)
#define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17)
#define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18)
#define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13)
#define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14)
#define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15)
#define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE UINT32_C(0x200)
#define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16)
#define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80)
#define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
#define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82)
#define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83)
#define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
#define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85)
#define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
#define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
#define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
#define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED UINT32_C(0x89)
#define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
#define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b)
#define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
#define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f)
#define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90)
#define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
#define CMDQ_BASE_OPCODE_CREATE_QP_BATCH UINT32_C(0x94)
#define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95)
#define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
#define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
#define CREQ_BASE_TYPE_MASK UINT32_C(0x3f)
#define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
#define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
#define CREQ_BASE_V UINT32_C(0x1)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP UINT32_C(0x4)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_SRQ UINT32_C(0x8)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_GID UINT32_C(0x18)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_FUNC UINT32_C(0x83)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_VERSION UINT32_C(0x8b)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_SRQ_USED UINT32_C(0x1)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800)
#define CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000)
#define CREATE_QP_BATCH_DATA_TYPE_RC UINT32_C(0x2)
#define CREATE_QP_BATCH_DATA_TYPE_UD UINT32_C(0x4)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define CREATE_QP_BATCH_DATA_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
#define CREATE_QP_BATCH_DATA_TYPE_GSI UINT32_C(0x7)
#define CREATE_QP_BATCH_DATA_SQ_LVL_MASK UINT32_C(0xf)
#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_0 UINT32_C(0x0)
#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_1 UINT32_C(0x1)
#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 UINT32_C(0x2)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CREATE_QP_BATCH_DATA_RQ_LVL_MASK UINT32_C(0xf)
#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_0 UINT32_C(0x0)
#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_1 UINT32_C(0x1)
#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 UINT32_C(0x2)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CREATE_QP_BATCH_DATA_SQ_SGE_MASK UINT32_C(0xf)
#define CREATE_QP_BATCH_DATA_SQ_FWO_MASK UINT32_C(0xfff0)
#define CREATE_QP_BATCH_DATA_RQ_SGE_MASK UINT32_C(0xf)
#define CREATE_QP_BATCH_DATA_RQ_FWO_MASK UINT32_C(0xfff0)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
#define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
#define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b)
#define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80)
#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
#define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION UINT32_C(0x4)
#define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x8)
#define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT UINT32_C(0x10)
#define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K UINT32_C(0x0)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K UINT32_C(0x2)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K UINT32_C(0x3)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K UINT32_C(0x4)
#define RX_PKT_COMPRESS_CMPL_V1 UINT32_C(0x1)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K UINT32_C(0x5)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K UINT32_C(0x6)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K UINT32_C(0x7)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M UINT32_C(0x8)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M UINT32_C(0x9)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M UINT32_C(0xa)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M UINT32_C(0xb)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M UINT32_C(0xc)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M UINT32_C(0xd)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M UINT32_C(0xe)
#define RX_PKT_COMPRESS_CMPL_UNUSED_MASK UINT32_C(0xe)
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M UINT32_C(0xf)
#define CMDQ_INITIALIZE_FW_RSVD_MASK UINT32_C(0xfff0)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK UINT32_C(0xff0)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR UINT32_C(0x10)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR UINT32_C(0x20)
#define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1)
#define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80)
#define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR UINT32_C(0x40)
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR UINT32_C(0x80)
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1)
#define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
#define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1)
#define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC UINT32_C(0x100)
#define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
#define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
#define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
#define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
#define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
#define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40)
#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80)
#define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100)
#define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200)
#define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400)
#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800)
#define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000)
#define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2)
#define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4)
#define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
#define CMDQ_CREATE_QP_TYPE_GSI UINT32_C(0x7)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC UINT32_C(0x200)
#define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC UINT32_C(0x400)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0)
#define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0)
#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC UINT32_C(0x800)
#define RX_PKT_COMPRESS_CMPL_METADATA1_MASK UINT32_C(0xf000)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
#define CREQ_CREATE_QP_RESP_V UINT32_C(0x1)
#define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
#define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
#define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
#define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1)
#define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
#define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3)
#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
#define CMDQ_MODIFY_QP_FLAGS_SRQ_USED UINT32_C(0x1)
#define CMDQ_MODIFY_QP_FLAGS_EXCLUDE_QP_UDCC UINT32_C(0x2)
#define CMDQ_MODIFY_QP_QP_TYPE_RC UINT32_C(0x2)
#define CMDQ_MODIFY_QP_QP_TYPE_UD UINT32_C(0x4)
#define RX_PKT_COMPRESS_CMPL_METADATA1_VALID UINT32_C(0x8000)
#define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
#define CMDQ_MODIFY_QP_QP_TYPE_GSI UINT32_C(0x7)
#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1)
#define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2)
#define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4)
#define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8)
#define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10)
#define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20)
#define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40)
#define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80)
#define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100)
#define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200)
#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400)
#define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE UINT32_C(0x800)
#define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000)
#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff)
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000)
#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE UINT32_C(0x1000)
#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000)
#define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf)
#define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0)
#define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1)
#define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2)
#define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3)
#define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4)
#define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5)
#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000)
#define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6)
#define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
#define CMDQ_MODIFY_QP_UNUSED1 UINT32_C(0x20)
#define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0)
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6)
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6)
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6)
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff)
#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1)
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2)
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4)
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK UINT32_C(0xffff)
#define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3)
#define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc)
#define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE UINT32_C(0x1)
#define CMDQ_MODIFY_QP_UNUSED3_MASK UINT32_C(0xe)
#define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4)
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4)
#define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1)
#define CMDQ_MODIFY_QP_UNUSED15_MASK UINT32_C(0xfffe)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK UINT32_C(0x1f0000)
#define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff)
#define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000)
#define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000)
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK UINT32_C(0x1fe00000)
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID UINT32_C(0x2)
#define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1)
#define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3)
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED UINT32_C(0x1)
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK UINT32_C(0xe)
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE UINT32_C(0x10)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK UINT32_C(0x1e00000)
#define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4)
#define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 21)
#define CREQ_QUERY_QP_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4)
#define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4)
#define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf)
#define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0)
#define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1)
#define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2)
#define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3)
#define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4)
#define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5)
#define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6)
#define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
#define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK UINT32_C(0xe0)
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff)
#define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1)
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2)
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4)
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 21)
#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12)
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 21)
#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
#define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1)
#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff)
#define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000)
#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 21)
#define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
#define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK UINT32_C(0xff)
#define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK UINT32_C(0xffff00)
#define CMDQ_QUERY_QP_EXTEND_VF_VALID UINT32_C(0x1000000)
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 21)
#define CREQ_QUERY_QP_EXTEND_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND UINT32_C(0x91)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK UINT32_C(0xf)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET UINT32_C(0x0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT UINT32_C(0x1)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR UINT32_C(0x2)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS UINT32_C(0x3)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD UINT32_C(0x4)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE UINT32_C(0x5)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 21)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR UINT32_C(0x6)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK UINT32_C(0xf0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 UINT32_C(0x0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 21)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 21)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK UINT32_C(0xf)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET UINT32_C(0x0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT UINT32_C(0x1)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR UINT32_C(0x2)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS UINT32_C(0x3)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD UINT32_C(0x4)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE UINT32_C(0x5)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR UINT32_C(0x6)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 21)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK UINT32_C(0xf0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 UINT32_C(0x0)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
#define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5)
#define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe000000)
#define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3)
#define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
#define CMDQ_CREATE_SRQ_UNUSED11_MASK UINT32_C(0xffe0)
#define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff)
#define CMDQ_CREATE_SRQ_UNUSED4_MASK UINT32_C(0xf000)
#define CMDQ_CREATE_SRQ_SRQ_FWO_MASK UINT32_C(0xfff)
#define CMDQ_CREATE_SRQ_SRQ_SGE_MASK UINT32_C(0xf000)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 25)
#define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1)
#define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 25)
#define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6)
#define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 25)
#define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6)
#define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK UINT32_C(0xffff)
#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000)
#define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8)
#define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 25)
#define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8)
#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8)
#define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 25)
#define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1)
#define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x2)
#define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE UINT32_C(0x4)
#define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID UINT32_C(0x8)
#define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3)
#define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 25)
#define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
#define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
#define CMDQ_CREATE_CQ_UNUSED27_MASK UINT32_C(0xffffffe0)
#define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff)
#define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x6) << 25)
#define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK UINT32_C(0x1ff)
#define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK UINT32_C(0x3e00)
#define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK UINT32_C(0x7c000)
#define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE UINT32_C(0x80000)
#define CMDQ_CREATE_CQ_UNUSED12_MASK UINT32_C(0xfff00000)
#define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x7) << 25)
#define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1)
#define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9)
#define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa)
#define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR UINT32_C(0x10000000)
#define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1)
#define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa)
#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK UINT32_C(0xe0000000)
#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3)
#define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc)
#define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3)
#define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffffe0)
#define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1)
#define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc)
#define CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ UINT32_C(0x90)
#define CMDQ_MODIFY_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_HANDLE UINT32_C(0x1)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_CNQ_ID UINT32_C(0x2)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_FCO UINT32_C(0x4)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_DPI UINT32_C(0x8)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_SIZE UINT32_C(0x10)
#define CMDQ_MODIFY_CQ_MODIFY_MASK_PBL UINT32_C(0x20)
#define CMDQ_MODIFY_CQ_CNQ_ID_MASK UINT32_C(0xfff)
#define CMDQ_MODIFY_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
#define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MODIFY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_MODIFY_CQ_RESP_V UINT32_C(0x1)
#define CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ UINT32_C(0x9)
#define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
#define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
#define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID UINT32_C(0x10)
#define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define CMDQ_ALLOCATE_MRW_UNUSED3_MASK UINT32_C(0xe0)
#define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20)
#define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1)
#define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
#define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK UINT32_C(0xf0)
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1)
#define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf)
#define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1)
#define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID UINT32_C(0x2)
#define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO UINT32_C(0x4)
#define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3)
#define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2)
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2)
#define CMDQ_REGISTER_MR_UNUSED1 UINT32_C(0x80)
#define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1)
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2)
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4)
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
#define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10)
#define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16)
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e)
#define CMDQ_REGISTER_MR_UNUSED11_MASK UINT32_C(0xffe0)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1)
#define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf)
#define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10)
#define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1)
#define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11)
#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff)
#define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
#define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
#define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
#define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000)
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK UINT32_C(0xffff)
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
#define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define CREQ_ADD_GID_RESP_V UINT32_C(0x1)
#define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
#define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12)
#define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define CREQ_DELETE_GID_RESP_V UINT32_C(0x1)
#define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12)
#define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17)
#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
#define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
#define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000)
#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
#define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1)
#define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
#define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18)
#define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QUERY_GID_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18)
#define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18)
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff)
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000)
#define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13)
#define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1)
#define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
#define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
#define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1)
#define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0)
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1)
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
#define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0)
#define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf)
#define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0)
#define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1)
#define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13)
#define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14)
#define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1)
#define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14)
#define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15)
#define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0)
#define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2)
#define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3)
#define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff)
#define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000)
#define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1)
#define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_CREATE_AH_RESP_V UINT32_C(0x1)
#define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15)
#define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16)
#define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
#define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1)
#define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16)
#define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID UINT32_C(0x1)
#define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
#define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID UINT32_C(0x2)
#define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK UINT32_C(0xff)
#define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK UINT32_C(0xffff00)
#define CMDQ_QUERY_ROCE_STATS_VF_VALID UINT32_C(0x1000000)
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QUERY_ROCE_STATS_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS UINT32_C(0x92)
#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID UINT32_C(0x1)
#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID UINT32_C(0x2)
#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK UINT32_C(0xff)
#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK UINT32_C(0xffff00)
#define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID UINT32_C(0x1000000)
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83)
#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83)
#define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1)
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK UINT32_C(0xe)
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (UINT32_C(0x0) << 1)
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (UINT32_C(0x1) << 1)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1)
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (UINT32_C(0x3) << 1)
#define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10)
#define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20)
#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x40)
#define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80)
#define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE UINT32_C(0x100)
#define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200)
#define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400)
#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED UINT32_C(0x800)
#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID UINT32_C(0x1000)
#define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED UINT32_C(0x2000)
#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
#define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED UINT32_C(0x4000)
#define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY UINT32_C(0x8000)
#define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
#define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED UINT32_C(0x1)
#define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED UINT32_C(0x2)
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED UINT32_C(0x4)
#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED UINT32_C(0x8)
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED UINT32_C(0x10)
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED UINT32_C(0x20)
#define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED UINT32_C(0x40)
#define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
#define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED UINT32_C(0x80)
#define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x1)
#define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED UINT32_C(0x2)
#define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED UINT32_C(0x4)
#define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED UINT32_C(0x8)
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK UINT32_C(0x30)
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (UINT32_C(0x0) << 4)
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (UINT32_C(0x1) << 4)
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (UINT32_C(0x2) << 4)
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
#define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1)
#define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1)
#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
#define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82)
#define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1)
#define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82)
#define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85)
#define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
#define CMDQ_READ_CONTEXT_TYPE_QPC UINT32_C(0x0)
#define CMDQ_READ_CONTEXT_TYPE_CQ UINT32_C(0x1)
#define CMDQ_READ_CONTEXT_TYPE_MRW UINT32_C(0x2)
#define CMDQ_READ_CONTEXT_TYPE_SRQ UINT32_C(0x3)
#define CREQ_READ_CONTEXT_TYPE_MASK UINT32_C(0x3f)
#define CREQ_READ_CONTEXT_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_READ_CONTEXT_V UINT32_C(0x1)
#define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85)
#define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
#define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
#define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff)
#define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000)
#define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff)
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
#define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1)
#define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
#define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
#define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
#define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK UINT32_C(0xfe)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7)
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8)
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0)
#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff)
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff)
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK UINT32_C(0xfe)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK UINT32_C(0x3)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK UINT32_C(0xf8)
#define RX_TPA_START_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK UINT32_C(0xc0)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK UINT32_C(0x3fff)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK UINT32_C(0xc000)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK UINT32_C(0x3ff)
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK UINT32_C(0xfc00)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
#define RX_TPA_START_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 UINT32_C(0x2)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000)
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000)
#define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000)
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
#define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe)
#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3)
#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc)
#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7)
#define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8)
#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
#define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0)
#define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff)
#define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000)
#define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff)
#define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00)
#define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0)
#define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR UINT32_C(0x8)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR UINT32_C(0x10)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT UINT32_C(0x200)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE UINT32_C(0x400)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP UINT32_C(0x800)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000)
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000)
#define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK UINT32_C(0xfe)
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK UINT32_C(0x3)
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK UINT32_C(0xf8)
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK UINT32_C(0xffc0)
#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK UINT32_C(0x3fff)
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK UINT32_C(0xc000)
#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK UINT32_C(0x3ff)
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK UINT32_C(0xfc00)
#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0)
#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE UINT32_C(0x4)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES UINT32_C(0x8)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS UINT32_C(0x10)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE UINT32_C(0x20)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH UINT32_C(0x40)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH UINT32_C(0x80)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH UINT32_C(0x100)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT UINT32_C(0x200)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR UINT32_C(0x400)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH UINT32_C(0x800)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN UINT32_C(0x1000)
#define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS UINT32_C(0x2000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN UINT32_C(0x4000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN UINT32_C(0x8000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC UINT32_C(0x10000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH UINT32_C(0x20000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH UINT32_C(0x40000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN UINT32_C(0x80000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX UINT32_C(0x100000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX UINT32_C(0x200000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND UINT32_C(0x400000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR UINT32_C(0x800000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR UINT32_C(0x1000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH UINT32_C(0x2000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV UINT32_C(0x4000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH UINT32_C(0x8000000)
#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS UINT32_C(0x10000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO UINT32_C(0x20000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH UINT32_C(0x40000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 UINT32_C(0x80000000)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 UINT32_C(0x100000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE UINT32_C(0x200000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT UINT32_C(0x400000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH UINT32_C(0x800000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 UINT32_C(0x1000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 UINT32_C(0x2000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES UINT32_C(0x4000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN UINT32_C(0x8000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH UINT32_C(0x10000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN UINT32_C(0x20000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN UINT32_C(0x40000000000)L
#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN UINT32_C(0x80000000000)L
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX UINT32_C(0x1)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR UINT32_C(0x2)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR UINT32_C(0x4)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP UINT32_C(0x8)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM UINT32_C(0x10)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR UINT32_C(0x20)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000)
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000)
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1)
#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f)
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN UINT32_C(0x1)
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP UINT32_C(0x2)
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP UINT32_C(0x4)
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE UINT32_C(0x8)
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID UINT32_C(0x10)
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE UINT32_C(0x1)
#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK UINT32_C(0xfe)
#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK UINT32_C(0xf)
#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK UINT32_C(0xf0)
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD UINT32_C(0x4)
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_SET_LINK_AGGR_MODE_RESP_V UINT32_C(0x1)
#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f)
#define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
#define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
#define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_MASK UINT32_C(0xf)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_NATIVE_QID_RANGE UINT32_C(0x0)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_EXTENDED_QID_RANGE UINT32_C(0x1)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_NATIVE_QID_RANGE UINT32_C(0x2)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE UINT32_C(0x3)
#define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_MASK UINT32_C(0xf0)
#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_V UINT32_C(0x1)
#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
#define CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH UINT32_C(0x94)
#define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
#define CREQ_CREATE_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_CREATE_QP_BATCH_RESP_V UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
#define CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH UINT32_C(0x94)
#define CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define CREQ_DESTROY_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
#define CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DESTROY_QP_BATCH_RESP_V UINT32_C(0x1)
#define CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH UINT32_C(0x95)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
#define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1)
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
#define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
#define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1)
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
#define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V UINT32_C(0x1)
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
#define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO UINT32_C(0x4)
#define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f)
#define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a)
#define CREQ_FUNC_EVENT_V UINT32_C(0x1)
#define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1)
#define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2)
#define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3)
#define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4)
#define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5)
#define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6)
#define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7)
#define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8)
#define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9)
#define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa)
#define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb)
#define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80)
#define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81)
#define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0)
#define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1)
#define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2)
#define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3)
#define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4)
#define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5)
#define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6)
#define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7)
#define CREQ_QP_EVENT_V UINT32_C(0x1)
#define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1)
#define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2)
#define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3)
#define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4)
#define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
#define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5)
#define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6)
#define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8)
#define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9)
#define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa)
#define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc)
#define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd)
#define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
#define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf)
#define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11)
#define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12)
#define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17)
#define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18)
#define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13)
#define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14)
#define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15)
#define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16)
#define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80)
#define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
#define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82)
#define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83)
#define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
#define CREQ_QP_EVENT_EVENT_READ_CONTEXT UINT32_C(0x85)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
#define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b)
#define CREQ_QP_EVENT_EVENT_MODIFY_CC UINT32_C(0x8c)
#define CREQ_QP_EVENT_EVENT_QUERY_CC UINT32_C(0x8d)
#define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e)
#define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f)
#define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND UINT32_C(0x91)
#define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
#define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR UINT32_C(0x1)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT UINT32_C(0x2)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT UINT32_C(0x3)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 UINT32_C(0x4)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 UINT32_C(0x5)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 UINT32_C(0x6)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 UINT32_C(0x7)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR UINT32_C(0x8)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR UINT32_C(0x9)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH UINT32_C(0xa)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP UINT32_C(0xb)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND UINT32_C(0xc)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG UINT32_C(0xd)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE UINT32_C(0xe)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR UINT32_C(0xf)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR UINT32_C(0x10)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR UINT32_C(0x11)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR UINT32_C(0x12)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR UINT32_C(0x13)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR UINT32_C(0x14)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x15)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR UINT32_C(0x16)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR UINT32_C(0x17)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR UINT32_C(0x18)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR UINT32_C(0x19)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR UINT32_C(0x1a)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR UINT32_C(0x1b)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR UINT32_C(0x1c)
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW UINT32_C(0x1d)
#define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1)
#define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX UINT32_C(0x1)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH UINT32_C(0x2)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE UINT32_C(0x3)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR UINT32_C(0x4)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT UINT32_C(0x5)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY UINT32_C(0x6)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR UINT32_C(0x7)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION UINT32_C(0x8)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR UINT32_C(0x9)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY UINT32_C(0xa)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR UINT32_C(0xb)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION UINT32_C(0xc)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR UINT32_C(0xd)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW UINT32_C(0xe)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE UINT32_C(0xf)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC UINT32_C(0x10)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE UINT32_C(0x11)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR UINT32_C(0x12)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR UINT32_C(0x13)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR UINT32_C(0x14)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY UINT32_C(0x15)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR UINT32_C(0x16)
#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR UINT32_C(0x17)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x18)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR UINT32_C(0x19)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR UINT32_C(0x1b)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR UINT32_C(0x1c)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND UINT32_C(0x1d)
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW UINT32_C(0x1e)
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT UINT32_C(0x38)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR UINT32_C(0x1)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR UINT32_C(0x2)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x3)
#define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR UINT32_C(0x4)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR UINT32_C(0x5)
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x6)
#define CREQ_CQ_ERROR_NOTIFICATION_V UINT32_C(0x1)
#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
#define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0)
#define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
#define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
#define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
#define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6)
#define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
#define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
#define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
#define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd)
#define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe)
#define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf)
#define SQ_BASE_WQE_TYPE_SEND_V3 UINT32_C(0x10)
#define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
#define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
#define SQ_BASE_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
#define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
#define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
#define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
#define SQ_BASE_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
#define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
#define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
#define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
#define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
#define SQ_BASE_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
#define SQ_BASE_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
#define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
#define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
#define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
#define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000)
#define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
#define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000)
#define SQ_PSN_SEARCH_EXT_START_PSN_MASK UINT32_C(0xffffff)
#define SQ_PSN_SEARCH_EXT_OPCODE_MASK UINT32_C(0xff000000)
#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK UINT32_C(0xffffff)
#define SQ_PSN_SEARCH_EXT_FLAGS_MASK UINT32_C(0xff000000)
#define SQ_MSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
#define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0)
#define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
#define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_SEND_FLAGS_SE UINT32_C(0x8)
#define SQ_SEND_FLAGS_INLINE UINT32_C(0x10)
#define SQ_SEND_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
#define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
#define SQ_SEND_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_SEND_HDR_WQE_TYPE_SEND UINT32_C(0x0)
#define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
#define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_SEND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_V2 UINT32_C(0x1)
#define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define RX_TPA_START_V2_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define SQ_SEND_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_SEND_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_SEND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_HDR_DST_QP_MASK UINT32_C(0xffffff)
#define SQ_SEND_HDR_AVID_MASK UINT32_C(0xfffff)
#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define SQ_SEND_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0)
#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8)
#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10)
#define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4)
#define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8)
#define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND UINT32_C(0x0)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE UINT32_C(0x10)
#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC UINT32_C(0x4)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP UINT32_C(0x8)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE UINT32_C(0x1000)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
#define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
#define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6)
#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RDMA_FLAGS_SE UINT32_C(0x8)
#define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RDMA_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RDMA_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_RDMA_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
#define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
#define SQ_RDMA_HDR_WQE_TYPE_READ_WQE UINT32_C(0x6)
#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_RDMA_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RDMA_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_RDMA_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RDMA_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_RDMA_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
#define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8)
#define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10)
#define SQ_ATOMIC_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_ATOMIC_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_TYPE_MASK UINT32_C(0x3f)
#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_ATOMIC_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_ATOMIC_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_ATOMIC_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
#define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define RX_TPA_START_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8)
#define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10)
#define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd)
#define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PMR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PMR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define HWRM_VER_GET UINT32_C(0x0)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0)
#define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
#define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
#define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
#define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR UINT32_C(0xd)
#define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_FR_PMR_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PMR_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_ZERO_BASED UINT32_C(0x20)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0)
#define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
#define SQ_FR_PPMR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
#define SQ_FR_PPMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define SQ_FR_PPMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PPMR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_FR_PPMR_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PPMR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PPMR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PPMR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PPMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PPMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PPMR_ZERO_BASED UINT32_C(0x20)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PPMR_PROXY_VF_VALID UINT32_C(0x20)
#define SQ_FR_PPMR_NUMLEVELS_MASK UINT32_C(0xc0)
#define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define SQ_FR_PPMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
#define SQ_FR_PPMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
#define SQ_FR_PPMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
#define SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
#define SQ_FR_PPMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_FR_PPMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PPMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_FR_PPMR_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PPMR_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PPMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PPMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PPMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define HWRM_RESERVED1 UINT32_C(0x10)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PPMR_HDR_ZERO_BASED UINT32_C(0x20)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define HWRM_FUNC_RESET UINT32_C(0x11)
#define RX_TPA_START_V3_CMPL_V1 UINT32_C(0x1)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define RX_TPA_START_V3_CMPL_UNUSED1_MASK UINT32_C(0x7e)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PPMR_HDR_PROXY_VF_VALID UINT32_C(0x20)
#define SQ_FR_PPMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0)
#define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
#define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
#define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
#define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe)
#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define HWRM_FUNC_GETFID UINT32_C(0x12)
#define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_BIND_FLAGS_SE UINT32_C(0x8)
#define SQ_BIND_FLAGS_INLINE UINT32_C(0x10)
#define SQ_BIND_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_BIND_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff)
#define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_BIND_ZERO_BASED UINT32_C(0x1)
#define SQ_BIND_MW_TYPE UINT32_C(0x2)
#define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
#define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
#define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
#define SQ_BIND_HDR_WQE_TYPE_BIND UINT32_C(0xe)
#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
#define SQ_BIND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_BIND_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_BIND_HDR_FLAGS_SE UINT32_C(0x8)
#define SQ_BIND_HDR_FLAGS_INLINE UINT32_C(0x10)
#define SQ_BIND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_BIND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff)
#define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define HWRM_FUNC_VF_FREE UINT32_C(0x14)
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_BIND_HDR_ZERO_BASED UINT32_C(0x1)
#define SQ_BIND_HDR_MW_TYPE UINT32_C(0x2)
#define SQ_BIND_HDR_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
#define SQ_BIND_HDR_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
#define SQ_MSN_SEARCH_V3_START_PSN_MASK UINT32_C(0xffffff)
#define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK UINT32_C(0xffffff000000)L
#define SQ_MSN_SEARCH_V3_START_IDX_MASK UINT32_C(0xffff000000000000)L
#define HWRM_FUNC_QCAPS UINT32_C(0x15)
#define SQ_MSN_SEARCH_V3_SGNLD UINT32_C(0x1)
#define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE UINT32_C(0x2)
#define SQ_SEND_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10)
#define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
#define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
#define SQ_SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_SEND_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_SEND_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_FUNC_QCFG UINT32_C(0x16)
#define SQ_SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define SQ_SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10)
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
#define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_SEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define HWRM_FUNC_CFG UINT32_C(0x17)
#define SQ_SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define SQ_SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
#define RX_TPA_START_V3_CMPL_AGG_ID_MASK UINT32_C(0xfff)
#define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define HWRM_FUNC_QSTATS UINT32_C(0x18)
#define RX_TPA_START_V3_CMPL_METADATA1_MASK UINT32_C(0xf000)
#define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RAWQP1SEND_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_RAWQP1SEND_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
#define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
#define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC UINT32_C(0x4)
#define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
#define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
#define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20)
#define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
#define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE UINT32_C(0x1000)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define RX_TPA_START_V3_CMPL_METADATA1_VALID UINT32_C(0x8000)
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
#define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC UINT32_C(0x4)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC UINT32_C(0x100)
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC UINT32_C(0x200)
#define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
#define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE UINT32_C(0x1000)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
#define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
#define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
#define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define SQ_UDSEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_UDSEND_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_UDSEND_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_UDSEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_UDSEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_UDSEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define SQ_UDSEND_V3_DST_QP_MASK UINT32_C(0xffffff)
#define SQ_UDSEND_V3_AVID_MASK UINT32_C(0x3ff)
#define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
#define SQ_UDSEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_UDSEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_UDSEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
#define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define SQ_UDSEND_HDR_V3_DST_QP_MASK UINT32_C(0xffffff)
#define SQ_UDSEND_HDR_V3_AVID_MASK UINT32_C(0x3ff)
#define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
#define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
#define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
#define SQ_RDMA_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define HWRM_PORT_PHY_CFG UINT32_C(0x20)
#define SQ_RDMA_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RDMA_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_RDMA_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RDMA_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RDMA_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_RDMA_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_RDMA_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define SQ_RDMA_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define HWRM_PORT_MAC_CFG UINT32_C(0x21)
#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
#define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
#define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_RDMA_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_RDMA_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_RDMA_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define SQ_RDMA_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
#define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_ATOMIC_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_ATOMIC_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_ATOMIC_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_ATOMIC_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_PORT_TS_QUERY UINT32_C(0x22)
#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
#define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_ATOMIC_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_ATOMIC_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define HWRM_PORT_QSTATS UINT32_C(0x23)
#define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
#define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
#define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_LOCALINVALIDATE_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE UINT32_C(0x400)
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO UINT32_C(0x800)
#define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
#define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PMR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_FR_PMR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PMR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PMR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_FR_PMR_V3_ZERO_BASED UINT32_C(0x40)
#define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define HWRM_PORT_CLR_STATS UINT32_C(0x25)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5)
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5)
#define SQ_FR_PMR_V3_NUMLEVELS_MASK UINT32_C(0xc00)
#define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10)
#define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10)
#define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10)
#define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
#define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define RX_TPA_START_V3_CMPL_V2 UINT32_C(0x1)
#define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
#define RX_TPA_START_V3_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define SQ_FR_PMR_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_FR_PMR_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_FR_PMR_HDR_V3_ZERO_BASED UINT32_C(0x40)
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
#define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5)
#define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5)
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5)
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK UINT32_C(0xc00)
#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10)
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10)
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10)
#define SQ_BIND_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define SQ_BIND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_BIND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_BIND_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_BIND_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_BIND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_BIND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_BIND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_BIND_V3_ZERO_BASED UINT32_C(0x40)
#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define SQ_BIND_V3_MW_TYPE UINT32_C(0x80)
#define SQ_BIND_V3__TYPE1 (UINT32_C(0x0) << 7)
#define SQ_BIND_V3__TYPE2 (UINT32_C(0x1) << 7)
#define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
#define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
#define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
#define RX_TPA_START_V3_CMPL_METADATA0_DE UINT32_C(0x1000)
#define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_BIND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_BIND_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
#define SQ_BIND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_BIND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_BIND_HDR_V3_ZERO_BASED UINT32_C(0x40)
#define SQ_BIND_HDR_V3_MW_TYPE UINT32_C(0x80)
#define SQ_BIND_HDR_V3__TYPE1 (UINT32_C(0x0) << 7)
#define SQ_BIND_HDR_V3__TYPE2 (UINT32_C(0x1) << 7)
#define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
#define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
#define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE UINT32_C(0x8)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
#define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
#define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80)
#define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
#define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff)
#define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80)
#define RQ_WQE_HDR_WR_ID_MASK UINT32_C(0xfffff)
#define RQ_WQE_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
#define HWRM_PORT_LED_CFG UINT32_C(0x2d)
#define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
#define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
#define CQ_BASE_TOGGLE UINT32_C(0x1)
#define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
#define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
#define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
#define CQ_BASE_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
#define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define CQ_BASE_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1)
#define CQ_BASE_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1)
#define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
#define CQ_BASE_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1)
#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1)
#define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1)
#define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
#define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
#define CQ_BASE_STATUS_OK UINT32_C(0x0)
#define CQ_BASE_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
#define CQ_BASE_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
#define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6)
#define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
#define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
#define CQ_BASE_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9)
#define CQ_BASE_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa)
#define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb)
#define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc)
#define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_BASE_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
#define CQ_BASE_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define CQ_REQ_TOGGLE UINT32_C(0x1)
#define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
#define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
#define CQ_REQ_PUSH UINT32_C(0x20)
#define CQ_REQ_STATUS_OK UINT32_C(0x0)
#define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
#define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3)
#define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4)
#define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
#define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7)
#define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8)
#define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9)
#define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa)
#define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
#define CQ_RES_RC_TOGGLE UINT32_C(0x1)
#define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
#define CQ_RES_RC_STATUS_OK UINT32_C(0x0)
#define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define HWRM_QUEUE_QCFG UINT32_C(0x31)
#define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
#define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_RC_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_RC_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_RC_FLAGS_INV UINT32_C(0x4)
#define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8)
#define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
#define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_UD_CFA_METADATA_VID_MASK UINT32_C(0xfff)
#define CQ_RES_UD_CFA_METADATA_DE UINT32_C(0x1000)
#define CQ_RES_UD_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_UD_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
#define HWRM_QUEUE_CFG UINT32_C(0x32)
#define CQ_RES_UD_STATUS_OK UINT32_C(0x0)
#define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_FLAGS_SRQ_RQ UINT32_C(0x0)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define CQ_RES_UD_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_UD_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
#define CQ_RES_UD_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
#define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6)
#define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
#define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
#define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
#define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00)
#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
#define CQ_RES_UD_V2_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
#define CQ_RES_UD_V2_CFA_METADATA0_DE UINT32_C(0x1000)
#define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
#define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID UINT32_C(0x400)
#define CQ_RES_UD_V2_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_V2_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_UD_V2_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
#define CQ_RES_UD_V2_STATUS_OK UINT32_C(0x0)
#define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
#define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define CQ_RES_UD_V2_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_UD_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_V2_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_V2_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
#define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
#define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
#define CQ_RES_UD_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
#define CQ_RES_UD_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
#define CQ_RES_UD_CFA_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK UINT32_C(0xfff)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define CQ_RES_UD_CFA_CFA_METADATA_DE UINT32_C(0x1000)
#define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define CQ_RES_UD_CFA_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_CFA_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
#define CQ_RES_UD_CFA_STATUS_OK UINT32_C(0x0)
#define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
#define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define CQ_RES_UD_CFA_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00)
#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
#define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
#define CQ_RES_UD_CFA_V2_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE UINT32_C(0x1000)
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_CFA_V2_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
#define CQ_RES_UD_CFA_V2_STATUS_OK UINT32_C(0x0)
#define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_V2_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
#define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
#define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
#define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
#define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
#define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
#define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK UINT32_C(0xffff)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
#define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0)
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1)
#define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
#define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
#define HWRM_VNIC_ALLOC UINT32_C(0x40)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define HWRM_VNIC_FREE UINT32_C(0x41)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE UINT32_C(0x1000)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define HWRM_VNIC_CFG UINT32_C(0x42)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
#define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define CQ_RES_RAWETH_QP1_V2_TOGGLE UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
#define CQ_RES_RAWETH_QP1_V2_STATUS_OK UINT32_C(0x0)
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define HWRM_VNIC_QCFG UINT32_C(0x43)
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
#define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
#define CQ_TERMINAL_TOGGLE UINT32_C(0x1)
#define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
#define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
#define CQ_TERMINAL_STATUS_OK UINT32_C(0x0)
#define CQ_CUTOFF_TOGGLE UINT32_C(0x1)
#define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
#define CQ_CUTOFF_RESIZE_TOGGLE_MASK UINT32_C(0x60)
#define CQ_CUTOFF_STATUS_OK UINT32_C(0x0)
#define CQ_NO_OP_TOGGLE UINT32_C(0x1)
#define CQ_NO_OP_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_NO_OP_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1)
#define CQ_NO_OP_STATUS_OK UINT32_C(0x0)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1)
#define CQ_REQ_V3_TOGGLE UINT32_C(0x1)
#define CQ_REQ_V3_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_REQ_V3_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1)
#define CQ_REQ_V3_PUSH UINT32_C(0x20)
#define CQ_REQ_V3_STATUS_OK UINT32_C(0x0)
#define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
#define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7)
#define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
#define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
#define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9)
#define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa)
#define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb)
#define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc)
#define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_REQ_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
#define CQ_RES_RC_V3_TOGGLE UINT32_C(0x1)
#define CQ_RES_RC_V3_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1)
#define CQ_RES_RC_V3_STATUS_OK UINT32_C(0x0)
#define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
#define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6)
#define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
#define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
#define RX_TPA_V2_START_CMPL_TYPE_MASK UINT32_C(0x3f)
#define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
#define CQ_RES_RC_V3_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_RC_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_RC_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_RC_V3_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_RC_V3_FLAGS_INV UINT32_C(0x4)
#define CQ_RES_RC_V3_FLAGS_RDMA UINT32_C(0x8)
#define CQ_RES_RC_V3_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
#define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
#define CQ_RES_UD_V3_LENGTH_MASK UINT32_C(0x3fff)
#define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
#define CQ_RES_UD_V3_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_V3_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1)
#define RX_TPA_V2_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define CQ_RES_UD_V3_STATUS_OK UINT32_C(0x0)
#define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
#define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
#define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define RX_TPA_V2_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
#define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define CQ_RES_UD_V3_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_UD_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_V3_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_V3_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_RAWETH_QP1_V3_ERROR UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK UINT32_C(0x3c0)
#define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (UINT32_C(0x1) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (UINT32_C(0x2) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (UINT32_C(0x3) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (UINT32_C(0x4) << 6)
#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (UINT32_C(0x5) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (UINT32_C(0x7) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK UINT32_C(0xf000)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID UINT32_C(0x8000)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
#define HWRM_VNIC_QCAPS UINT32_C(0x4a)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE UINT32_C(0x1000)
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define HWRM_VNIC_UPDATE UINT32_C(0x4b)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE UINT32_C(0x400)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define CQ_RES_RAWETH_QP1_V3_TOGGLE UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK UINT32_C(0x1e)
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1)
#define CQ_RES_RAWETH_QP1_V3_STATUS_OK UINT32_C(0x0)
#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
#define HWRM_RING_ALLOC UINT32_C(0x50)
#define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
#define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT UINT32_C(0x800)
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_V3_LENGTH_MASK UINT32_C(0x3fff)
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
#define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE UINT32_C(0x1000)
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
#define CQ_RES_UD_CFA_V3_QID_MASK UINT32_C(0x7ff)
#define CQ_RES_UD_CFA_V3_UNUSED_MASK UINT32_C(0xff800)
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK UINT32_C(0xf00000)
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID UINT32_C(0x800000)
#define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
#define HWRM_RING_FREE UINT32_C(0x51)
#define CQ_RES_UD_CFA_V3_TOGGLE UINT32_C(0x1)
#define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK UINT32_C(0x1e)
#define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
#define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1)
#define CQ_RES_UD_CFA_V3_STATUS_OK UINT32_C(0x0)
#define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
#define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
#define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
#define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
#define CQ_RES_UD_CFA_V3_FLAGS_IMM UINT32_C(0x2)
#define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK UINT32_C(0xc)
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
#define NQ_BASE_TYPE_MASK UINT32_C(0x3f)
#define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
#define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
#define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
#define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
#define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
#define NQ_BASE_TYPE_NQ_REASSIGN UINT32_C(0x3c)
#define NQ_BASE_INFO10_MASK UINT32_C(0xffc0)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
#define NQ_BASE_V UINT32_C(0x1)
#define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe)
#define NQ_CN_TYPE_MASK UINT32_C(0x3f)
#define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
#define NQ_CN_TOGGLE_MASK UINT32_C(0xc0)
#define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
#define NQ_CN_V UINT32_C(0x1)
#define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f)
#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32)
#define NQ_SRQ_EVENT_TOGGLE_MASK UINT32_C(0xc0)
#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1)
#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
#define NQ_SRQ_EVENT_V UINT32_C(0x1)
#define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f)
#define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34)
#define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1)
#define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf)
#define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff)
#define NQ_DBQ_EVENT_V UINT32_C(0x1)
#define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff)
#define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000)
#define NQ_REASSIGN_TYPE_MASK UINT32_C(0x3f)
#define NQ_REASSIGN_TYPE_NQ_REASSIGN UINT32_C(0x3c)
#define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
#define NQ_REASSIGN_V UINT32_C(0x1)
#define XRRQ_IRRQ_TYPE UINT32_C(0x1)
#define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0)
#define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
#define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800)
#define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff)
#define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff)
#define XRRQ_ORRQ_TYPE UINT32_C(0x1)
#define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0)
#define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
#define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
#define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800)
#define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff)
#define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff)
#define PTU_PTE_VALID UINT32_C(0x1)
#define PTU_PTE_LAST UINT32_C(0x2)
#define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4)
#define PTU_PTE_UNUSED_MASK UINT32_C(0xff8)
#define PTU_PTE_PAGE_MASK UINT32_C(0xfffffffffffff000)L
#define PTU_PDE_VALID UINT32_C(0x1)
#define PTU_PDE_UNUSED_MASK UINT32_C(0xffe)
#define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
#define PTU_PDE_PAGE_MASK UINT32_C(0xfffffffffffff000)L
#define DBC_DBC_INDEX_MASK UINT32_C(0xffffff)
#define DBC_DBC_EPOCH UINT32_C(0x1000000)
#define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000)
#define DBC_DBC_XID_MASK UINT32_C(0xfffff)
#define DBC_DBC_PATH_MASK UINT32_C(0x3000000)
#define DBC_DBC_PATH_ROCE (UINT32_C(0x0) << 24)
#define DBC_DBC_PATH_L2 (UINT32_C(0x1) << 24)
#define DBC_DBC_PATH_ENGINE (UINT32_C(0x2) << 24)
#define DBC_DBC_VALID UINT32_C(0x4000000)
#define DBC_DBC_DEBUG_TRACE UINT32_C(0x8000000)
#define DBC_DBC_TYPE_MASK UINT32_C(0xf0000000)
#define HWRM_RING_RESET UINT32_C(0x5e)
#define DBC_DBC_TYPE_SQ (UINT32_C(0x0) << 28)
#define DBC_DBC_TYPE_RQ (UINT32_C(0x1) << 28)
#define DBC_DBC_TYPE_SRQ (UINT32_C(0x2) << 28)
#define DBC_DBC_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
#define DBC_DBC_TYPE_CQ (UINT32_C(0x4) << 28)
#define DBC_DBC_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
#define DBC_DBC_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
#define DBC_DBC_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
#define DBC_DBC_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
#define DBC_DBC_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
#define DBC_DBC_TYPE_NQ (UINT32_C(0xa) << 28)
#define DBC_DBC_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
#define DBC_DBC_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
#define DBC_DBC_TYPE_NULL (UINT32_C(0xf) << 28)
#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
#define DBC_DBC64_INDEX_MASK UINT32_C(0xffffff)
#define DBC_DBC64_EPOCH UINT32_C(0x1000000)
#define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
#define DBC_DBC64_TOGGLE_MASK UINT32_C(0x6000000)
#define DBC_DBC64_XID_MASK UINT32_C(0xfffff00000000)L
#define DBC_DBC64_PATH_MASK UINT32_C(0x300000000000000)L
#define DBC_DBC64_PATH_ROCE (UINT32_C(0x0)L << 56)
#define DBC_DBC64_PATH_L2 (UINT32_C(0x1)L << 56)
#define DBC_DBC64_PATH_ENGINE (UINT32_C(0x2)L << 56)
#define DBC_DBC64_VALID UINT32_C(0x400000000000000)L
#define DBC_DBC64_DEBUG_TRACE UINT32_C(0x800000000000000)L
#define DBC_DBC64_TYPE_MASK UINT32_C(0xf000000000000000)L
#define HWRM_RING_GRP_FREE UINT32_C(0x61)
#define DBC_DBC64_TYPE_SQ (UINT32_C(0x0)L << 60)
#define DBC_DBC64_TYPE_RQ (UINT32_C(0x1)L << 60)
#define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
#define DBC_DBC64_TYPE_SRQ (UINT32_C(0x2)L << 60)
#define DBC_DBC64_TYPE_SRQ_ARM (UINT32_C(0x3)L << 60)
#define DBC_DBC64_TYPE_CQ (UINT32_C(0x4)L << 60)
#define DBC_DBC64_TYPE_CQ_ARMSE (UINT32_C(0x5)L << 60)
#define DBC_DBC64_TYPE_CQ_ARMALL (UINT32_C(0x6)L << 60)
#define DBC_DBC64_TYPE_CQ_ARMENA (UINT32_C(0x7)L << 60)
#define DBC_DBC64_TYPE_SRQ_ARMENA (UINT32_C(0x8)L << 60)
#define DBC_DBC64_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9)L << 60)
#define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
#define DBC_DBC64_TYPE_NQ (UINT32_C(0xa)L << 60)
#define DBC_DBC64_TYPE_NQ_ARM (UINT32_C(0xb)L << 60)
#define DBC_DBC64_TYPE_NQ_MASK (UINT32_C(0xe)L << 60)
#define DBC_DBC64_TYPE_NULL (UINT32_C(0xf)L << 60)
#define HWRM_RING_CFG UINT32_C(0x62)
#define DBC_DBC32_XID_MASK UINT32_C(0xfffff)
#define DBC_DBC32_PATH_MASK UINT32_C(0xc00000)
#define DBC_DBC32_PATH_ROCE (UINT32_C(0x0) << 22)
#define DBC_DBC32_PATH_L2 (UINT32_C(0x1) << 22)
#define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
#define DBC_DBC32_INCR_MASK UINT32_C(0xf000000)
#define DBC_DBC32_ABS UINT32_C(0x10000000)
#define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000)
#define DBC_DBC32_TYPE_SQ (UINT32_C(0x0) << 29)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
#define DB_PUSH_START_DB_INDEX_MASK UINT32_C(0xffffff)
#define DB_PUSH_START_DB_PI_LO_MASK UINT32_C(0xff000000)
#define HWRM_RING_QCFG UINT32_C(0x63)
#define DB_PUSH_START_DB_XID_MASK UINT32_C(0xfffff00000000)L
#define DB_PUSH_START_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L
#define DB_PUSH_START_DB_TYPE_MASK UINT32_C(0xf000000000000000)L
#define DB_PUSH_START_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60)
#define DB_PUSH_START_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
#define DB_PUSH_END_DB_INDEX_MASK UINT32_C(0xffffff)
#define DB_PUSH_END_DB_PI_LO_MASK UINT32_C(0xff000000)
#define DB_PUSH_END_DB_XID_MASK UINT32_C(0xfffff00000000)L
#define DB_PUSH_END_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L
#define DB_PUSH_END_DB_PATH_MASK UINT32_C(0x300000000000000)L
#define DB_PUSH_END_DB_PATH_ROCE (UINT32_C(0x0)L << 56)
#define DB_PUSH_END_DB_PATH_L2 (UINT32_C(0x1)L << 56)
#define DB_PUSH_END_DB_PATH_ENGINE (UINT32_C(0x2)L << 56)
#define DB_PUSH_END_DB_DEBUG_TRACE UINT32_C(0x800000000000000)L
#define DB_PUSH_END_DB_TYPE_MASK UINT32_C(0xf000000000000000)L
#define DB_PUSH_END_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60)
#define DB_PUSH_END_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60)
#define DB_PUSH_INFO_PUSH_INDEX_MASK UINT32_C(0xffffff)
#define DB_PUSH_INFO_PUSH_SIZE_MASK UINT32_C(0x1f000000)
#define HWRM_RESERVED5 UINT32_C(0x64)
#define DBC_ABSOLUTE_DB_32_INDEX_MASK UINT32_C(0xffff)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
#define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000)
#define DBC_ABSOLUTE_DB_32_TOGGLE_MASK UINT32_C(0x60000)
#define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0x1f80000)
#define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x6000000)
#define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 25)
#define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 25)
#define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x8000000)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
#define DBC_ABSOLUTE_DB_32_TYPE_MASK UINT32_C(0xf0000000)
#define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
#define DBC_ABSOLUTE_DB_32_TYPE_NULL (UINT32_C(0xf) << 28)
#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
#define DBC_RELATIVE_DB_32_XID_MASK UINT32_C(0xfffff)
#define DBC_RELATIVE_DB_32_PATH_MASK UINT32_C(0xc00000)
#define DBC_RELATIVE_DB_32_PATH_ROCE (UINT32_C(0x0) << 22)
#define DBC_RELATIVE_DB_32_PATH_L2 (UINT32_C(0x1) << 22)
#define DBC_RELATIVE_DB_32_INCR_MASK UINT32_C(0x1f000000)
#define HWRM_RESERVED6 UINT32_C(0x65)
#define DBC_RELATIVE_DB_32_TYPE_MASK UINT32_C(0xe0000000)
#define DBC_RELATIVE_DB_32_TYPE_SQ (UINT32_C(0x0) << 29)
#define DBC_RELATIVE_DB_32_TYPE_SRQ (UINT32_C(0x1) << 29)
#define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
#define DBC_RELATIVE_DB_32_TYPE_CQ (UINT32_C(0x2) << 29)
#define DBC_RELATIVE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x3) << 29)
#define DBC_RELATIVE_DB_32_TYPE_NQ (UINT32_C(0x4) << 29)
#define DBC_RELATIVE_DB_32_TYPE_NQ_ARM (UINT32_C(0x5) << 29)
#define DBC_RELATIVE_DB_32_TYPE_NQ_MASK (UINT32_C(0x6) << 29)
#define DBC_DRK_VALID UINT32_C(0x1)
#define DBC_DRK_LAST UINT32_C(0x2)
#define DBC_DRK_LINKED UINT32_C(0x4)
#define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
#define DBC_DRK_DB_FORMAT UINT32_C(0x8)
#define DBC_DRK_DB_FORMAT_B64 (UINT32_C(0x0) << 3)
#define DBC_DRK_DB_FORMAT_B32A (UINT32_C(0x1) << 3)
#define DBC_DRK_STRIDE_MASK UINT32_C(0x300)
#define DBC_DRK_STRIDE_OFF (UINT32_C(0x0) << 8)
#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
#define DBC_DRK_STRIDE_SZ64 (UINT32_C(0x1) << 8)
#define DBC_DRK_STRIDE_SZ128 (UINT32_C(0x2) << 8)
#define DBC_DRK_SIZE_MASK UINT32_C(0xc00)
#define DBC_DRK_SIZE_FOUR (UINT32_C(0x0) << 10)
#define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
#define DBC_DRK_SIZE_ONE (UINT32_C(0x1) << 10)
#define DBC_DRK_SIZE_TWO (UINT32_C(0x2) << 10)
#define DBC_DRK_SIZE_THREE (UINT32_C(0x3) << 10)
#define DBC_DRK_PI_MASK UINT32_C(0xffff)
#define DBC_DRK64_VALID UINT32_C(0x1)
#define DBC_DRK64_LAST UINT32_C(0x2)
#define DBC_DRK64_LINKED UINT32_C(0x4)
#define DBC_DRK64_DB_FORMAT UINT32_C(0x8)
#define DBC_DRK64_DB_FORMAT_B64 (UINT32_C(0x0) << 3)
#define DBC_DRK64_DB_FORMAT_B32A (UINT32_C(0x1) << 3)
#define DBC_DRK64_STRIDE_MASK UINT32_C(0x300)
#define DBC_DRK64_STRIDE_OFF (UINT32_C(0x0) << 8)
#define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
#define DBC_DRK64_STRIDE_SZ64 (UINT32_C(0x1) << 8)
#define DBC_DRK64_STRIDE_SZ128 (UINT32_C(0x2) << 8)
#define DBC_DRK64_SIZE_MASK UINT32_C(0xc00)
#define DBC_DRK64_SIZE_FOUR (UINT32_C(0x0) << 10)
#define DBC_DRK64_SIZE_ONE (UINT32_C(0x1) << 10)
#define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
#define DBC_DRK64_SIZE_TWO (UINT32_C(0x2) << 10)
#define DBC_DRK64_SIZE_THREE (UINT32_C(0x3) << 10)
#define DBC_DRK64_PI_MASK UINT32_C(0xffff00000000)L
#define DBC_DBC_V3_INDEX_MASK UINT32_C(0xffffff)
#define DBC_DBC_V3_EPOCH UINT32_C(0x1000000)
#define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
#define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
#define DBC_DBC_V3_TOGGLE_MASK UINT32_C(0x6000000)
#define DBC_DBC_V3_XID_MASK UINT32_C(0xfff)
#define DBC_DBC_V3_PATH_MASK UINT32_C(0x3000000)
#define DBC_DBC_V3_PATH_ROCE (UINT32_C(0x0) << 24)
#define DBC_DBC_V3_PATH_L2 (UINT32_C(0x1) << 24)
#define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
#define DBC_DBC_V3_VALID UINT32_C(0x4000000)
#define DBC_DBC_V3_DEBUG_TRACE UINT32_C(0x8000000)
#define DBC_DBC_V3_TYPE_MASK UINT32_C(0xf0000000)
#define DBC_DBC_V3_TYPE_SQ (UINT32_C(0x0) << 28)
#define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
#define DBC_DBC_V3_TYPE_RQ (UINT32_C(0x1) << 28)
#define DBC_DBC_V3_TYPE_SRQ (UINT32_C(0x2) << 28)
#define DBC_DBC_V3_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
#define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define DBC_DBC_V3_TYPE_CQ (UINT32_C(0x4) << 28)
#define DBC_DBC_V3_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
#define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
#define DBC_DBC_V3_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
#define DBC_DBC_V3_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
#define DBC_DBC_V3_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
#define DBC_DBC_V3_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
#define DBC_DBC_V3_TYPE_NQ (UINT32_C(0xa) << 28)
#define RX_TPA_V2_START_CMPL_V2 UINT32_C(0x1)
#define DBC_DBC_V3_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
#define RX_TPA_V2_START_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define DBC_DBC_V3_TYPE_CQ_REASSIGN (UINT32_C(0xc) << 28)
#define DBC_DBC_V3_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
#define DBC_DBC_V3_TYPE_NULL (UINT32_C(0xf) << 28)
#define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
#define DBC_XP_XID_MASK UINT32_C(0xfff)
#define DBC_XP_DEBUG_TRACE UINT32_C(0x1000000)
#define DBC_XP_TYPE_MASK UINT32_C(0xf0000000)
#define DBC_XP_TYPE_SQ (UINT32_C(0x0) << 28)
#define DBC_XP_TYPE_RQ (UINT32_C(0x1) << 28)
#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define DBC_XP_TYPE_SRQ (UINT32_C(0x2) << 28)
#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
#define FW_STATUS_REG_CODE_MASK UINT32_C(0xffff)
#define FW_STATUS_REG_CODE_READY UINT32_C(0x8000)
#define FW_STATUS_REG_IMAGE_DEGRADED UINT32_C(0x10000)
#define FW_STATUS_REG_RECOVERABLE UINT32_C(0x20000)
#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define FW_STATUS_REG_CRASHDUMP_ONGOING UINT32_C(0x40000)
#define FW_STATUS_REG_CRASHDUMP_COMPLETE UINT32_C(0x80000)
#define FW_STATUS_REG_SHUTDOWN UINT32_C(0x100000)
#define FW_STATUS_REG_CRASHED_NO_MASTER UINT32_C(0x200000)
#define FW_STATUS_REG_RECOVERING UINT32_C(0x400000)
#define FW_STATUS_REG_MANU_DEBUG_STATUS UINT32_C(0x800000)
#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
#define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
#define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
#define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
#define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
#define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED UINT32_C(0x0)
#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED UINT32_C(0x1)
#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED UINT32_C(0x2)
#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED UINT32_C(0x3)
#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED UINT32_C(0x4)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8)
#define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
#define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
#define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0x7)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_EYE_PROJECTION UINT32_C(0x8)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88)
#define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK UINT32_C(0xf)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION UINT32_C(0x10)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_HORIZONTAL (UINT32_C(0x0) << 4)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL (UINT32_C(0x1) << 4)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE UINT32_C(0x20)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) << 5)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xc0)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E8 UINT32_C(0x0)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E9 UINT32_C(0x1)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START UINT32_C(0x1)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS UINT32_C(0x2)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP UINT32_C(0x3)
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1)
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_MASK UINT32_C(0xfe)
#define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a)
#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
#define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b)
#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRID UINT32_C(0x1)
#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2)
#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4)
#define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8)
#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_MAX_SPEED_SELECT UINT32_C(0x10)
#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_NOT_CONFIGURED UINT32_C(0x0)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_50G UINT32_C(0x1)
#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_100G UINT32_C(0x2)
#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_200G UINT32_C(0x3)
#define HWRM_QUEUE_QCAPS UINT32_C(0x8c)
#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRID UINT32_C(0x1)
#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2)
#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4)
#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8)
#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_MAX_SPEED_SELECT UINT32_C(0x10)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_NOT_CONFIGURED UINT32_C(0x0)
#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_50G UINT32_C(0x1)
#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_100G UINT32_C(0x2)
#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_200G UINT32_C(0x3)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d)
#define HWRM_MFG_OTP_QCFG_OUTPUT_ENABLES_BITMAP_MAX_SPEED UINT32_C(0x10)
#define HWRM_MFG_OTP_QCFG_OUTPUT_ENABLES_BITMAP_ENABLES_VALID UINT32_C(0x8000)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_INCREMENTAL UINT32_C(0x1)
#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_FIXED UINT32_C(0x2)
#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM UINT32_C(0x3)
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
#define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_START UINT32_C(0x1)
#define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_END UINT32_C(0x2)
#define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
#define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
#define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_INPUT_FLAGS_FORCE UINT32_C(0x1)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_ALREADY_LOCKED UINT32_C(0x1)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_NOT_EMPTY UINT32_C(0x2)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_FACT_CFG UINT32_C(0x4)
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_VPD UINT32_C(0x8)
#define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_IS_EMPTY UINT32_C(0x1)
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2)
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_MALFORMED_DATA UINT32_C(0x4)
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_NOT_LOCKED UINT32_C(0x8)
#define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
#define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
#define HWRM_MFG_PRVSN_EXPORT_CSR_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x2)
#define HWRM_MFG_PRVSN_IMPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
#define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_NOT_PROVISIONED UINT32_C(0x0)
#define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED UINT32_C(0x1)
#define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_LOCKED UINT32_C(0x2)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_STORAGE UINT32_C(0x3)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_CERT_VERIFY_FAIL UINT32_C(0x4)
#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT UINT32_C(0x5)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_INVALID UINT32_C(0x0)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM UINT32_C(0x1)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE UINT32_C(0xff)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_MASK UINT32_C(0xff)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_NOT_PROVISIONED UINT32_C(0x0)
#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED UINT32_C(0x1)
#define HWRM_MFG_PRVSN_EXPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
#define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_CERT_INVALID UINT32_C(0x2)
#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x3)
#define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_INVALID UINT32_C(0x0)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID UINT32_C(0x1)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_BOOTUP UINT32_C(0x0)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE UINT32_C(0x1)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA256 UINT32_C(0x0)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA384 UINT32_C(0x1)
#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA512 UINT32_C(0x2)
#define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PERIPHERAL_TEST UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_FLAGS_PERIPHERAL_TEST UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40)
#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80)
#define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PERIPHERAL_TEST UINT32_C(0x1)
#define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
#define RX_TPA_V2_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PERIPHERAL_TEST UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_EEPROM UINT32_C(0x2)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_MMCX UINT32_C(0x4)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_GNSS UINT32_C(0x8)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_PCIE UINT32_C(0x10)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_OCXO UINT32_C(0x40)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_TELECOM_PLL UINT32_C(0x80)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_MEMORY UINT32_C(0x1)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_EEPROM UINT32_C(0x2)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_MMCX UINT32_C(0x4)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_GNSS UINT32_C(0x8)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_PCIE UINT32_C(0x10)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_INTERNAL_FABRIC UINT32_C(0x20)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_OCXO UINT32_C(0x40)
#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_TELECOM_PLL UINT32_C(0x80)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_INVALID UINT32_C(0x0)
#define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG UINT32_C(0x1)
#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_INVALID UINT32_C(0x0)
#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW UINT32_C(0x1)
#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE UINT32_C(0x2)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_DESTINATION UINT32_C(0x0)
#define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP UINT32_C(0x1)
#define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1)
#define HWRM_UDCC_CFG_INPUT_ENABLES_UDCC_MODE UINT32_C(0x1)
#define HWRM_UDCC_CFG_INPUT_UDCC_MODE_DISABLED UINT32_C(0x0)
#define HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED UINT32_C(0x1)
#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SESSION_STATE UINT32_C(0x1)
#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_DEST_MAC UINT32_C(0x2)
#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SRC_MAC UINT32_C(0x4)
#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_TX_STATS_RECORD UINT32_C(0x8)
#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_RX_STATS_RECORD UINT32_C(0x10)
#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_ENABLED UINT32_C(0x1)
#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2)
#define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4)
#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_ENABLED UINT32_C(0x1)
#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2)
#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4)
#define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
#define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3)
#define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define RX_ABUF_CMPL_V UINT32_C(0x1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
#define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
#define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
#define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
#define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
#define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
#define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define VEE_FLUSH_V UINT32_C(0x1)
#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
#define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
#define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
#define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
#define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
#define EJECT_CMPL_V UINT32_C(0x1)
#define HWRM_RESERVED7 UINT32_C(0xba)
#define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
#define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
#define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
#define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
#define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
#define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_CMPL_V UINT32_C(0x1)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
#define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
#define HWRM_FW_SYNC UINT32_C(0xc3)
#define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
#define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
#define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
#define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
#define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
#define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
#define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
#define HWRM_FW_SET_TIME UINT32_C(0xc8)
#define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_FW_GET_TIME UINT32_C(0xc9)
#define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
#define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY UINT32_C(0x9)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG UINT32_C(0xa)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
#define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR UINT32_C(0x30)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE UINT32_C(0x35)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED UINT32_C(0x36)
#define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION UINT32_C(0x37)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ UINT32_C(0x38)
#define HWRM_FW_ECN_CFG UINT32_C(0xcd)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE UINT32_C(0x39)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE UINT32_C(0x3a)
#define HWRM_FW_ECN_QCFG UINT32_C(0xce)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE UINT32_C(0x3b)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE UINT32_C(0x3c)
#define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE UINT32_C(0x3d)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE UINT32_C(0x3e)
#define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE UINT32_C(0x3f)
#define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE UINT32_C(0x40)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE UINT32_C(0x41)
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST UINT32_C(0x42)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE UINT32_C(0x43)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP UINT32_C(0x44)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
#define HWRM_OEM_CMD UINT32_C(0xd4)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE UINT32_C(0x47)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE UINT32_C(0x48)
#define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR UINT32_C(0x4a)
#define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b)
#define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE UINT32_C(0x4d)
#define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE UINT32_C(0x4e)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE UINT32_C(0x4f)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP UINT32_C(0x50)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x51)
#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
#define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
#define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
#define HWRM_PORT_CFG UINT32_C(0xdc)
#define HWRM_PORT_QCFG UINT32_C(0xdd)
#define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
#define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN UINT32_C(0x0)
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP UINT32_C(0x1)
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0xe)
if (str & UINT32_C(0x80000000)) {
if (str & UINT32_C(1)) {