sys/dev/pci/drm/i915/gt/intel_timeline.c

229

memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));

sys/dev/pci/drm/i915/gt/intel_timeline.c

231

drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);

sys/dev/pci/drm/i915/gt/intel_timeline.c

311

u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES);

sys/dev/pci/drm/i915/gt/intel_timeline.c

314

if (TIMELINE_SEQNO_BYTES <= BIT(5) && (next_ofs & BIT(5)))

sys/dev/pci/drm/i915/gt/intel_timeline.c

69

timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES);

sys/dev/pci/drm/i915/gt/intel_timeline.c

70

drm_clflush_virt_range(vaddr + ofs, TIMELINE_SEQNO_BYTES);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1157

count < (PAGE_SIZE / TIMELINE_SEQNO_BYTES - 1) / 2);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

39

return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

63

#define CACHELINES_PER_PAGE (PAGE_SIZE / TIMELINE_SEQNO_BYTES / 2)