sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

584

return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K);

sys/dev/pci/drm/drm_file.c

891

if (sz == 0 || !IS_ALIGNED(sz, SZ_1K))

sys/dev/pci/drm/drm_file.c

893

sz = div_u64(sz, SZ_1K);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

86

bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);

sys/dev/pci/drm/i915/gt/intel_rc6.c

286

resource_size_t pctx_size = 32 * SZ_1K;

sys/dev/pci/drm/i915/gt/intel_rc6.c

308

resource_size_t pctx_size = 24 * SZ_1K;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

119

guc_wopcm_size / SZ_1K,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

120

(u32)(offset + sizeof(u32)) / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

138

(guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

173

guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,

sys/dev/pci/drm/i915/gt/intel_wopcm.c

174

size / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

182

guc_wopcm_size / SZ_1K, size / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

191

guc_wopcm_base / SZ_1K, size / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

259

guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);

sys/dev/pci/drm/i915/gt/intel_wopcm.c

312

guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

624

sz = min_t(u32, sz, (SZ_1K - rq->reserved_space) / sizeof(u32) -

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

802

(*fw)->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

18

#define PXP43_MAX_HECI_INOUT_SIZE (PAGE_ALIGN(SZ_64K + SZ_1K))