sys/arch/armv7/sunxi/sxiahci.c

118

SXISET4(sc, SXIAHCI_PHYCS1, 1 << 19);

sys/arch/armv7/sunxi/sxiahci.c

130

SXISET4(sc, SXIAHCI_PHYCS1, 1 << 28 | 1 << 15);

sys/arch/armv7/sunxi/sxiahci.c

140

SXISET4(sc, SXIAHCI_PHYCS0, 1 << 19);

sys/arch/armv7/sunxi/sxiahci.c

151

SXISET4(sc, SXIAHCI_PHYCS2, 1 << 24);

sys/arch/armv7/sunxi/sxie.c

300

SXISET4(sc, SXIE_INTSR, SXIE_INTR_CLEAR);

sys/arch/armv7/sunxi/sxie.c

353

SXISET4(sc, SXIE_MACCR0, SXIE_MACTXFC | SXIE_MACRXFC);

sys/arch/armv7/sunxi/sxie.c

396

SXISET4(sc, SXIE_INTSR, SXIE_INTR_CLEAR);

sys/arch/armv7/sunxi/sxie.c

398

SXISET4(sc, SXIE_RXCR, SXIE_RXFLUSH);

sys/arch/armv7/sunxi/sxie.c

420

SXISET4(sc, SXIE_CR, SXIE_RXTX_ENABLE);

sys/arch/armv7/sunxi/sxie.c

426

SXISET4(sc, SXIE_INTCR, SXIE_INTR_ENABLE);

sys/arch/armv7/sunxi/sxie.c

462

SXISET4(sc, SXIE_INTCR, SXIE_INTR_ENABLE);

sys/arch/armv7/sunxi/sxie.c

528

SXISET4(sc, SXIE_TXCR0 + (fifo * 4), 1);

sys/arch/armv7/sunxi/sxie.c

598

SXISET4(sc, SXIE_RXCR, SXIE_RXFLUSH);

sys/arch/armv7/sunxi/sxie.c

600

SXISET4(sc, SXIE_CR, SXIE_RX_ENABLE);

sys/dev/fdt/sxiccmu.c

2233

SXISET4(sc, reg, (1U << bit));

sys/dev/fdt/sxiccmu.c

2259

SXISET4(sc, reg, (1U << bit));

sys/dev/fdt/sxiccmu.c

867

SXISET4(sc, 0, CCU_SDx_SCLK_GATING);

sys/dev/fdt/sxiccmu.c

881

SXISET4(sc, reg * 4, (1U << bit));

sys/dev/fdt/sxiccmu.c

898

SXISET4(sc, reg * 4, (1U << bit));

sys/dev/fdt/sxirtc.c

199

SXISET4(sc, SXIRTC_LOSC_OUT_GATING, 1);