sys/arch/armv7/sunxi/sxiahci.c

133

SXICLR4(sc, SXIAHCI_PHYCS1, 1 << 19);

sys/arch/armv7/sunxi/sxiahci.c

179

SXICLR4(sc, SXIAHCI_CAP, AHCI_REG_CAP_SPM);

sys/arch/armv7/sunxi/sxie.c

401

SXICLR4(sc, SXIE_MACCR0, SXIE_MACSOFTRESET);

sys/arch/armv7/sunxi/sxie.c

597

SXICLR4(sc, SXIE_CR, SXIE_RX_ENABLE);

sys/dev/fdt/sxiccmu.c

2235

SXICLR4(sc, reg, (1U << bit));

sys/dev/fdt/sxiccmu.c

2257

SXICLR4(sc, reg, (1U << bit));

sys/dev/fdt/sxiccmu.c

869

SXICLR4(sc, 0, CCU_SDx_SCLK_GATING);

sys/dev/fdt/sxiccmu.c

883

SXICLR4(sc, reg * 4, (1U << bit));

sys/dev/fdt/sxiccmu.c

896

SXICLR4(sc, reg * 4, (1U << bit));

sys/dev/fdt/sxirtc.c

201

SXICLR4(sc, SXIRTC_LOSC_OUT_GATING, 1);