SXIREAD4
while ((SXIREAD4(sc, SXIAHCI_PHYCS0) >> 28 & 7) != 2 && --timo)
while ((SXIREAD4(sc, SXIAHCI_PHYCS2) & (1 << 24)) && --timo)
reg = SXIREAD4(sc, SXIE_MACA0);
reg = SXIREAD4(sc, SXIE_MACA1);
pending = SXIREAD4(sc, SXIE_INTSR);
fbc = SXIREAD4(sc, SXIE_RXFBC);
reg = SXIREAD4(sc, SXIE_RXIO);
while (SXIREAD4(sc, SXIE_RXCR) & SXIE_RXFLUSH);
reg = SXIREAD4(sc, SXIE_RXIO);
while (SXIREAD4(sc, SXIE_MACMIND) & 1 && --timo)
return SXIREAD4(sc, SXIE_MACMRDD) & 0xffff;
while (SXIREAD4(sc, SXIE_MACMIND) & 1 && --timo)
SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) | (bits))
SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) & ~(bits))
SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits))
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
reg = SXIREAD4(sc, A64_PLL_CPUX_CTRL_REG);
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
reg = SXIREAD4(sc, A80_AHB1_CLK_CFG_REG);
reg = SXIREAD4(sc, D1_PLL_CPU_CTRL_REG);
reg = SXIREAD4(sc, D1_RISCV_CLK_REG);
reg = SXIREAD4(sc, D1_PSI_CLK_REG);
reg = SXIREAD4(sc, H3_PLL_CPUX_CTRL_REG);
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
reg = SXIREAD4(sc, H3_AHB0_CLK_REG);
reg = SXIREAD4(sc, H3_APB0_CFG_REG);
reg = SXIREAD4(sc, H6_AHB3_CFG_REG);
reg = SXIREAD4(sc, H616_AHB3_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A64_PLL_CPUX_CTRL_REG);
while ((SXIREAD4(sc, A64_PLL_CPUX_CTRL_REG) &
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, offset);
reg = SXIREAD4(sc, H3_PLL_CPUX_CTRL_REG);
lock_time = SXIREAD4(sc, H3_PLL_STABLE_TIME_REG1);
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
reg = SXIREAD4(sc, offset);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, 0);
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
reg = SXIREAD4(sc, SXIPIO_DAT(port));
reg = SXIREAD4(sc, SXIPIO_DAT(port));
reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
reg = SXIREAD4(sc, SXIPIO_DAT(port));
reg = SXIREAD4(sc, sc->sc_yymmdd);
reg = SXIREAD4(sc, sc->sc_hhmmss);