sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1059

SW_MODE, &s->sw_mode);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

157

SW_MODE, info->gfx9.swizzle,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

526

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

276

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

474

type SW_MODE;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1290

SW_MODE, &s->sw_mode);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

322

SW_MODE, info->gfx9.swizzle,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

414

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

331

SW_MODE, info->gfx9.swizzle,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

342

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

70

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

54

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

565

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

592

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

982

SW_MODE, &s->sw_mode);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

65

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\