sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

39

SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

40

SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

41

SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

42

SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1000

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1001

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1002

SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1003

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1004

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1005

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1006

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1007

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1008

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1009

SRI_ARR(OTG_H_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1010

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1011

SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1012

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1013

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1014

SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1015

SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1016

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1017

SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1018

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1019

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1020

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1021

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1022

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1023

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1024

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1025

SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1026

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1027

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1028

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1029

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1030

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1031

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1032

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1033

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1034

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1035

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1036

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1037

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1038

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1039

SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1040

SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1041

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1042

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1043

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1044

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1045

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1046

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1048

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1049

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1050

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1051

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1052

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1053

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1054

SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1055

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1056

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1057

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1058

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1059

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1060

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1061

SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1062

SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1063

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1068

SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1069

SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1070

SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1071

SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1072

SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1074

SRI_ARR(DCHUBP_CNTL, HUBP, id), SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1075

SRI_ARR(HUBPREQ_DEBUG, HUBP, id), SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1076

SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1077

SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1078

SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1079

SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1080

SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1081

SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1082

SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1083

SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1084

SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1085

SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1086

SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1087

SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1088

SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1089

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1090

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1091

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1092

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1093

SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1094

SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1095

SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1096

SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1097

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1098

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1099

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1100

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1101

SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1102

SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1103

SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1104

SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1105

SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1106

SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1107

SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1108

SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1109

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1110

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1111

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1112

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1113

SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1114

SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1115

SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1116

SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1117

SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1118

SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1119

SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1120

SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1121

SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1122

SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1123

SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1124

SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1125

SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1126

SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1127

SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1128

SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1129

SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1130

SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1131

SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1132

SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1133

SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1134

SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1135

SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1136

SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1137

SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1138

SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1139

SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1140

SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1141

SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1142

SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1143

SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1144

SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1145

SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1148

SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1149

SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1150

SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1151

SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1152

SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1153

SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1154

SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1155

SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1156

SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1157

SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1158

SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1159

SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1160

SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1161

SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1162

SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1163

SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1164

SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1165

SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1166

SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1167

SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1168

SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1169

SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1170

SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1171

SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1172

SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1173

SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1175

HUBP_REG_LIST_DCN2_COMMON_RI(id), SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1176

SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1177

SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1178

SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1179

SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1180

SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1182

HUBP_REG_LIST_DCN21_RI(id), SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1184

HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1185

SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1186

SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1258

SRI_ARR(CNTL, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1259

SRI_ARR(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1260

SRI_ARR(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1261

SRI_ARR(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1262

SRI_ARR(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1263

SRI_ARR(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1264

SRI_ARR(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

215

SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

216

SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

217

SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

218

SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

219

SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

220

SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

221

SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

222

SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

223

SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

224

SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

225

SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

226

SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

230

SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

231

SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

242

SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

243

SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

244

SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

245

SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

246

SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

250

SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

251

SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

252

SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

253

SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

254

SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

255

SRI_ARR(AFMT_60958_0, AFMT, id), SRI_ARR(AFMT_60958_1, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

256

SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

260

SRI_ARR(APG_CONTROL, APG, id), SRI_ARR(APG_CONTROL2, APG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

261

SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

265

SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

266

SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

267

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

268

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

269

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

270

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

271

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

272

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

273

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

274

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

275

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

276

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

277

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

278

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

279

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

280

SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

281

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

282

SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

283

SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

284

SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

285

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

286

SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

287

SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

288

SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

289

SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

290

SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

291

SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

292

SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

293

SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

294

SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

295

SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

296

SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

297

SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

298

SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

299

SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

300

SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

301

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

302

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

303

SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

304

SRI_ARR(DME_CONTROL, DME, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

305

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

306

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

307

SRI_ARR(DIG_FE_CNTL, DIG, id), SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

308

SRI_ARR(DIG_FIFO_CTRL0, DIG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

313

SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

314

SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

317

AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

320

#define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

324

SRI_ARR(DIG_BE_CNTL, DIG, id), SRI_ARR(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

325

SRI_ARR(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

326

SRI_ARR(TMDS_DCBALANCER_CONTROL, DIG, id), SRI_ARR(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

327

SRI_ARR(DP_DPHY_CNTL, DP, id), SRI_ARR(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

328

SRI_ARR(DP_DPHY_SCRAM_CNTL, DP, id), SRI_ARR(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

329

SRI_ARR(DP_DPHY_SYM1, DP, id), SRI_ARR(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

330

SRI_ARR(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

331

SRI_ARR(DP_LINK_CNTL, DP, id), SRI_ARR(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

332

SRI_ARR(DP_MSE_SAT0, DP, id), SRI_ARR(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

333

SRI_ARR(DP_MSE_SAT2, DP, id), SRI_ARR(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

334

SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

335

SRI_ARR(DP_DPHY_FAST_TRAINING, DP, id), SRI_ARR(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

336

SRI_ARR(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

337

SRI_ARR(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

340

LE_DCN3_REG_LIST_RI(id), SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

355

SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

356

SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

357

SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

358

SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

359

SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

360

SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

361

SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

362

SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

363

SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

364

SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

365

SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

366

SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

367

SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

368

SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

369

SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

370

SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

371

SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

372

SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

373

SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

374

SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

375

SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

376

SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

377

SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

378

SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

379

SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

380

SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

381

SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

382

SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

383

SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

384

SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

385

SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

389

SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

390

SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

391

SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

392

SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

393

SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

394

SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

395

SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

396

SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

397

SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

398

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

399

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

400

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

401

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

402

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

403

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

404

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

405

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

406

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

407

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

408

SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

409

SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

410

SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

411

SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

412

SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

413

SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

414

SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

415

SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

416

SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

417

SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

421

SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

422

SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

423

SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

424

SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

425

SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

426

SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

427

SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

428

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

429

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

430

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

431

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

432

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

433

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

434

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

435

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

436

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

437

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

438

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

439

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

440

SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

441

SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

442

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

443

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

444

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

445

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

446

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

447

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

448

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

449

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

450

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

451

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

452

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

453

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

454

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

455

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

456

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

457

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

458

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

459

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

460

SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

461

SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

462

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

463

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

464

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

465

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

466

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

467

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

468

SRI_ARR(CM_GAMUT_REMAP_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

469

SRI_ARR(CM_GAMUT_REMAP_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

470

SRI_ARR(CM_GAMUT_REMAP_C13_C14, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

471

SRI_ARR(CM_GAMUT_REMAP_C21_C22, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

472

SRI_ARR(CM_GAMUT_REMAP_C23_C24, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

473

SRI_ARR(CM_GAMUT_REMAP_C31_C32, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

474

SRI_ARR(CM_GAMUT_REMAP_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

475

SRI_ARR(CM_GAMUT_REMAP_B_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

476

SRI_ARR(CM_GAMUT_REMAP_B_C13_C14, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

477

SRI_ARR(CM_GAMUT_REMAP_B_C21_C22, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

478

SRI_ARR(CM_GAMUT_REMAP_B_C23_C24, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

479

SRI_ARR(CM_GAMUT_REMAP_B_C31_C32, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

480

SRI_ARR(CM_GAMUT_REMAP_B_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

481

SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

482

SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

483

SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

484

SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

485

SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

486

SRI_ARR(DSCL_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

487

SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

488

SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

489

SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

490

SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

491

SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

492

SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

493

SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

494

SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

495

SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

496

SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

497

SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

498

SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

499

SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

500

SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

501

SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

502

SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

503

SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

504

SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

505

SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

506

SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

507

SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

508

SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

509

SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

510

SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

511

SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

512

SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

513

SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

514

SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

515

SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

516

SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

517

SRI_ARR(CURSOR0_COLOR0, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

518

SRI_ARR(CURSOR0_COLOR1, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

519

SRI_ARR(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

520

SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

521

SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

522

SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

523

SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

524

SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

525

SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

526

SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

527

SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

528

SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

529

SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

530

SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

531

SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

532

SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

533

SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

534

SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

535

SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

536

SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

537

SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

541

SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

542

SRI_ARR(FMT_DITHER_RAND_R_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

543

SRI_ARR(FMT_DITHER_RAND_G_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

544

SRI_ARR(FMT_DITHER_RAND_B_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

545

SRI_ARR(FMT_CLAMP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

546

SRI_ARR(FMT_DYNAMIC_EXP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

547

SRI_ARR(FMT_MAP420_MEMORY_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

548

SRI_ARR(OPPBUF_CONTROL, OPPBUF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

549

SRI_ARR(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

550

SRI_ARR(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

551

SRI_ARR(OPP_PIPE_CONTROL, OPP_PIPE, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

556

SRI_ARR(DPG_CONTROL, DPG, id), SRI_ARR(DPG_DIMENSIONS, DPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

557

SRI_ARR(DPG_OFFSET_SEGMENT, DPG, id), SRI_ARR(DPG_COLOUR_B_CB, DPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

558

SRI_ARR(DPG_COLOUR_G_Y, DPG, id), SRI_ARR(DPG_COLOUR_R_CR, DPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

559

SRI_ARR(DPG_RAMP_CONTROL, DPG, id), SRI_ARR(DPG_STATUS, DPG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

563

SRI_ARR(FMT_422_CONTROL, FMT, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

567

SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_ARB_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

568

SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

569

SRI_ARR(AUX_INTERRUPT_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

570

SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

571

SRI_ARR(AUX_SW_STATUS, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

725

SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

726

SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

727

SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

728

SRI_ARR(DSCC_STATUS, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

729

SRI_ARR(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

730

SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

731

SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

732

SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

733

SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

734

SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

735

SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

736

SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

737

SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

738

SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

739

SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

740

SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

741

SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

742

SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

743

SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

744

SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

745

SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

746

SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

747

SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

748

SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

749

SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

750

SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

751

SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

752

SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

753

SRI_ARR(DSCC_MEM_POWER_CONTROL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

754

SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

755

SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

756

SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

757

SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

758

SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

759

SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

760

SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

761

SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

762

SRI_ARR(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

763

SRI_ARR(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

764

SRI_ARR(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

765

SRI_ARR(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

766

SRI_ARR(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

767

SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

768

SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

769

SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

770

SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

771

SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

772

SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

773

SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

100

SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

101

SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

102

SRI_ARR(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

103

SRI_ARR(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

104

SRI_ARR(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

105

SRI_ARR(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

106

SRI_ARR(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

107

SRI_ARR(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

108

SRI_ARR(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

109

SRI_ARR(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

110

SRI_ARR(DP_MSA_VBID_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

111

SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

112

SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

113

SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

114

SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

115

SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

116

SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

117

SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

118

SRI_ARR(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

119

SRI_ARR(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

120

SRI_ARR(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

121

SRI_ARR(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

122

SRI_ARR(DP_SEC_CNTL5, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

123

SRI_ARR(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

124

SRI_ARR(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

125

SRI_ARR(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

126

SRI_ARR(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

127

SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

128

SRI_ARR(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

129

SRI_ARR(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

130

SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

131

SRI_ARR(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

132

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

133

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

134

SRI_ARR(DP_SEC_FRAMING4, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

135

SRI_ARR(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

136

SRI_ARR(DME_CONTROL, DME, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

137

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

138

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

139

SRI_ARR(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

140

SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

141

SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

142

SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

143

SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

144

SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

148

SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

155

SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

219

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

220

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

221

SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

222

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

223

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

224

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

225

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

226

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

227

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

228

SRI_ARR(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

229

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

230

SRI_ARR(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

231

SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

232

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

233

SRI_ARR(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

234

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

235

SRI_ARR(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

236

SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

237

SRI_ARR(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

238

SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

239

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

240

SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

241

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

242

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

243

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

244

SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

245

SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

246

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

247

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

248

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

249

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

250

SRI_ARR(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

251

SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

252

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

253

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

254

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

255

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

256

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

257

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

258

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

259

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

260

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

261

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

262

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

263

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

264

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

265

SRI_ARR(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

266

SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

267

SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

268

SRI_ARR(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

269

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

270

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

271

SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

272

SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

273

SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

274

SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

275

SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

276

SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

277

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

278

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

279

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

280

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

281

SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

282

SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

283

SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

284

SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

285

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

286

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

287

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

288

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

289

SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

290

SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

291

SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

292

SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

294

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

295

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

296

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

297

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

298

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

299

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

300

SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

301

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

302

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

303

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

304

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

305

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

306

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

307

SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

309

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

53

SRI_ARR(FMT_422_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

54

SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

61

SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

62

SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

63

SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

64

SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

65

SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

66

SRI_ARR(VPG_MEM_PWR, VPG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

69

SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

70

SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

71

SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

72

SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

73

SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

74

SRI_ARR(AFMT_60958_0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

75

SRI_ARR(AFMT_60958_1, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

76

SRI_ARR(AFMT_60958_2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

77

SRI_ARR(AFMT_MEM_PWR, AFMT, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

81

SRI_ARR(AFMT_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

82

SRI_ARR(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

83

SRI_ARR(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

84

SRI_ARR(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

85

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

86

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

87

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

88

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

89

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

90

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

91

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

92

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

93

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

94

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

95

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

96

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

97

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

98

SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

99

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

100

SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

101

SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

102

SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

103

SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

104

SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

105

SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

106

SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

107

SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

108

SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

109

SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

110

SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

111

SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

112

SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

113

SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

114

SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

115

SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

116

SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

117

SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

118

SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

119

SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

120

SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

121

SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

122

SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

123

SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

124

SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

125

SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

126

SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

127

SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

128

SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

129

SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

130

SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

131

SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

132

SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

133

SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

134

SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

135

SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

136

SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

137

SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

138

SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

139

SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

140

SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

142

SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

143

SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

144

SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

148

SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

149

SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

150

SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

151

SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

152

SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

153

SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

154

SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

155

SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

156

SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

157

SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

158

SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

159

SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

160

SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

161

SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

162

SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

163

SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

164

SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

165

SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

166

SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

167

SRI_ARR(DC_ABM1_ACE_THRES_DATA, ABM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

173

SRI_ARR(VPG_MEM_PWR, VPG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

177

SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

178

SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

179

SRI_ARR(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

180

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

181

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

182

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

183

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

184

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

185

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

186

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

187

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

188

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

189

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

190

SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

191

SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

192

SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

193

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

194

SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

195

SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

196

SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

197

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

198

SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

199

SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

200

SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

201

SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

202

SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

203

SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

204

SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

205

SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

206

SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

207

SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

208

SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

209

SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

210

SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

211

SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

212

SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

213

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

214

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

215

SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

216

SRI_ARR(DME_CONTROL, DME, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

217

SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

218

SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

219

SRI_ARR(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

220

SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

221

SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

222

SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

223

SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

224

SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

229

SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

230

SRI_ARR(DIG_BE_CLK_CNTL, DIG, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

234

SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

235

SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

236

SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

237

SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

238

SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

239

SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

240

SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

241

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

242

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

243

SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

244

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

245

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

246

SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

247

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

248

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

249

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

250

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

251

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

252

SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

253

SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

254

SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

255

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

256

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

257

SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

258

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

259

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

260

SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

261

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

262

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

263

SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

264

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

265

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

266

SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

267

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

268

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

269

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

270

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

271

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

272

SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

273

SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

274

SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

275

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

276

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

277

SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

278

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

279

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

280

SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

281

SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

282

SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

283

SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

284

SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

285

SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

286

SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

287

SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

288

SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

289

SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

290

SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

291

SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

292

SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

293

SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

294

SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

295

SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

296

SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

297

SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

298

SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

299

SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

300

SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

301

SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

302

SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

303

SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

304

SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

305

SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

306

SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

307

SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

308

SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

309

SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

310

SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

311

SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

312

SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

313

SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

314

SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

315

SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

316

SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

317

SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

318

SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

319

SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

320

SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

321

SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

322

SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

323

SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

324

SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

325

SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

326

SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

327

SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

328

SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

329

SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

330

SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

331

SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

332

SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

333

SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

334

SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

335

SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

336

SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

337

SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

338

SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

339

SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

340

SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

341

SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

342

SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

343

SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

344

SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

345

SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

346

SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

347

SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

348

SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

349

SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

35

SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

350

SRI_ARR(DSCL_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

351

SRI_ARR(DSCL_SC_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

352

SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

353

SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

354

SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

355

SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

356

SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

357

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

358

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

359

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

36

SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

360

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

361

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

362

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

363

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

364

SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

365

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

366

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

367

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

368

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

369

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

37

SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

370

SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

371

SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

372

SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

373

SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

374

SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

375

SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

376

SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

377

SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

378

SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

379

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

38

SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

380

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

381

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

382

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

383

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

384

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

385

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

386

SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

387

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

388

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

389

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

39

SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

390

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

391

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

392

SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

393

SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

394

SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

395

SRI_ARR(ISHARP_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

396

SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

397

SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

398

SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

399

SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

40

SRI_ARR(DCHUBP_CNTL, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

400

SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

401

SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

402

SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

403

SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

404

SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

405

SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

406

SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

407

SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

408

SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

409

SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

41

SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

414

SRI_ARR(FMT_422_CONTROL, FMT, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

418

SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

419

SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

42

SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

420

SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

421

SRI_ARR(DSCC_STATUS, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

422

SRI_ARR(DSCC_INTERRUPT_CONTROL0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

423

SRI_ARR(DSCC_INTERRUPT_CONTROL1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

424

SRI_ARR(DSCC_INTERRUPT_STATUS0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

425

SRI_ARR(DSCC_INTERRUPT_STATUS1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

426

SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

427

SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

428

SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

429

SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

43

SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

430

SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

431

SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

432

SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

433

SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

434

SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

435

SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

436

SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

437

SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

438

SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

439

SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

44

SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

440

SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

441

SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

442

SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

443

SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

444

SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

445

SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

446

SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

447

SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

448

SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

449

SRI_ARR(DSCC_MEM_POWER_CONTROL0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

45

SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

450

SRI_ARR(DSCC_MEM_POWER_CONTROL1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

451

SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

452

SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

453

SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

454

SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

455

SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

456

SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

457

SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

458

SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

459

SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

46

SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

460

SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

461

SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

462

SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

463

SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

464

SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

465

SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

47

SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

479

SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

48

SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

480

SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

481

SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

482

SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

483

SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

484

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

485

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

486

SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

487

SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

488

SRI_ARR(OTG_H_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

489

SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

49

SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

490

SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

491

SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

492

SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

493

SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

494

SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

495

SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

496

SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

497

SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

498

SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

499

SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

50

SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

500

SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

501

SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

502

SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

503

SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

504

SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

505

SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

506

SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

507

SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

508

SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

509

SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

51

SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

510

SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

511

SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

512

SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

513

SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

514

SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

515

SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

516

SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

517

SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

518

SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

519

SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

52

SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

520

SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

521

SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

522

SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

523

SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

524

SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

525

SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

527

SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

528

SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

529

SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

53

SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

530

SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

531

SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

532

SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

533

SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

534

SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

535

SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

536

SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

537

SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

538

SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

539

SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

54

SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

540

SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

541

SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

542

SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

543

SRI_ARR(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

55

SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

56

SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

57

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

58

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

59

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

60

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

61

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

62

SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

63

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

64

SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

65

SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

66

SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

67

SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

68

SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

69

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

70

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

71

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

72

SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

73

SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

74

SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

75

SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

76

SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

77

SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

78

SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

79

SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

80

SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

81

SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

82

SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

83

SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

84

SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

85

SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

86

SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

87

SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

88

SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

89

SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

90

SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

91

SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

92

SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

93

SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

94

SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

95

SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

96

SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

97

SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

98

SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

99

SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \