sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

101

SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

102

SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

103

SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

104

SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

105

SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

106

SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

107

SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

108

SRI(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

109

SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

110

SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

111

SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

112

SRI(DC_ABM1_ACE_THRES_12, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

117

SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

118

SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

119

SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

120

SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

121

SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

122

SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

123

SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

124

SRI(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

125

SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

126

SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

127

SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

128

SRI(DC_ABM1_ACE_THRES_12, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

55

SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

56

SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

57

SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

58

SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

59

SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

60

SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

61

SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

62

SRI(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

63

SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

64

SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

65

SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

66

SRI(DC_ABM1_ACE_THRES_12, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

87

SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

88

SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

89

SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

90

SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

91

SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

92

SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

93

SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

94

SRI(BL1_PWM_USER_LEVEL, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

95

SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

96

SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

31

SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

32

SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

35

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

36

SRI(AUX_ARB_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

37

SRI(AUX_SW_DATA, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

38

SRI(AUX_SW_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

39

SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

40

SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

41

SRI(AUX_SW_STATUS, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

44

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

45

SRI(AUX_ARB_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

46

SRI(AUX_SW_DATA, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

47

SRI(AUX_SW_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

48

SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

49

SRI(AUX_SW_STATUS, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

104

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

119

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

134

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

152

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

175

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

34

SRI(RESYNC_CNTL, PIXCLK, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

35

SRI(PLL_CNTL, BPHYC_PLL, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

38

SRI(RESYNC_CNTL, PIXCLK, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

39

SRI(PLL_CNTL, DCCG_PLL, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

42

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

59

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

80

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

89

SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

85

SRI(SETUP, DC_I2C_DDC, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

86

SRI(SPEED, DC_I2C_DDC, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

87

SRI(HW_STATUS, DC_I2C_DDC, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

35

SRI(CUR_UPDATE, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

36

SRI(CUR_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

37

SRI(CUR_POSITION, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

38

SRI(CUR_HOT_SPOT, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

39

SRI(CUR_COLOR1, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

40

SRI(CUR_COLOR2, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

41

SRI(CUR_SIZE, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

42

SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

43

SRI(CUR_SURFACE_ADDRESS, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

44

SRI(PRESCALE_GRPH_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

45

SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

46

SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

47

SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

48

SRI(INPUT_GAMMA_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

49

SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

50

SRI(DC_LUT_RW_MODE, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

51

SRI(DC_LUT_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

52

SRI(DC_LUT_RW_INDEX, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

53

SRI(DC_LUT_SEQ_COLOR, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

54

SRI(DEGAMMA_CONTROL, DCP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

58

SRI(DCFE_MEM_PWR_CTRL, CRTC, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

62

SRI(DCFE_MEM_PWR_CTRL, DCFE, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

100

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

101

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

102

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

103

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

104

SRI(DP_SEC_CNTL1, DP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

108

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

113

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

114

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

119

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

120

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

121

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

126

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

127

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

132

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

133

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

134

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

40

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

41

SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

42

SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

45

SRI(DC_HPD_CONTROL, HPD, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

52

SRI(DIG_BE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

53

SRI(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

54

SRI(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

55

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

56

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

57

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

58

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

59

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

60

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

61

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

62

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

63

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

64

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

65

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

66

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

67

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

68

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

69

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

70

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

71

SRI(DP_SEC_CNTL1, DP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

75

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

76

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

81

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

86

SRI(DIG_BE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

87

SRI(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

88

SRI(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

89

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

90

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

91

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

92

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

93

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

94

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

95

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

96

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

97

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

98

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

99

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

101

SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

102

SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

103

SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

35

SRI(GRPH_ENABLE, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

36

SRI(GRPH_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

37

SRI(GRPH_X_START, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

38

SRI(GRPH_Y_START, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

39

SRI(GRPH_X_END, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

40

SRI(GRPH_Y_END, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

41

SRI(GRPH_PITCH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

42

SRI(HW_ROTATION, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

43

SRI(GRPH_SWAP_CNTL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

44

SRI(PRESCALE_GRPH_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

45

SRI(GRPH_UPDATE, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

46

SRI(GRPH_FLIP_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

47

SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

48

SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

49

SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

50

SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

51

SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

52

SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

53

SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

54

SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

55

SRI(DMIF_BUFFER_CONTROL, PIPE, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

58

SRI(DVMM_PTE_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

59

SRI(DVMM_PTE_ARB_CONTROL, DCP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

63

SRI(GRPH_ENABLE, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

64

SRI(GRPH_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

65

SRI(GRPH_X_START, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

66

SRI(GRPH_Y_START, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

67

SRI(GRPH_X_END, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

68

SRI(GRPH_Y_END, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

69

SRI(GRPH_PITCH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

70

SRI(GRPH_SWAP_CNTL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

71

SRI(PRESCALE_GRPH_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

72

SRI(GRPH_UPDATE, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

73

SRI(GRPH_FLIP_CONTROL, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

74

SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

75

SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

76

SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

77

SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

78

SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

79

SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

80

SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

81

SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

82

SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

83

SRI(DMIF_BUFFER_CONTROL, PIPE, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

88

SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

92

SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

44

SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

45

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

46

SRI(FMT_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

47

SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

48

SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

49

SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

50

SRI(FMT_CLAMP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

51

SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

52

SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

53

SRI(FMT_CLAMP_COMPONENT_B, FMT, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

57

SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

58

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

59

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

63

SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

64

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

65

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

69

SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

70

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

71

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

75

SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

76

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

77

SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

78

SRI(CONTROL, FMT_MEMORY, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

82

SRI(CONTROL, FMT_MEMORY, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

86

SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

87

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

88

SRI(FMT_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

89

SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

90

SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

91

SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

92

SRI(FMT_CLAMP_CNTL, FMT, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

102

SRI(AFMT_CNTL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

103

SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

104

SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

105

SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

106

SRI(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

107

SRI(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

108

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

109

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

110

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

111

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

112

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

113

SRI(HDMI_DB_CONTROL, DIG, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

44

SRI(AFMT_AVI_INFO0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

45

SRI(AFMT_AVI_INFO1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

46

SRI(AFMT_AVI_INFO2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

47

SRI(AFMT_AVI_INFO3, DIG, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

50

SRI(AFMT_GENERIC_0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

51

SRI(AFMT_GENERIC_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

52

SRI(AFMT_GENERIC_2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

53

SRI(AFMT_GENERIC_3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

54

SRI(AFMT_GENERIC_4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

55

SRI(AFMT_GENERIC_5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

56

SRI(AFMT_GENERIC_6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

57

SRI(AFMT_GENERIC_7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

58

SRI(AFMT_GENERIC_HDR, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

59

SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

60

SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

61

SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

62

SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

63

SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

64

SRI(AFMT_60958_0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

65

SRI(AFMT_60958_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

66

SRI(AFMT_60958_2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

67

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

68

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

69

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

70

SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

71

SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

72

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

73

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

74

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

75

SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

76

SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

77

SRI(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

78

SRI(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

79

SRI(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

80

SRI(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

81

SRI(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

82

SRI(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

83

SRI(TMDS_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

84

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

85

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

86

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

87

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

88

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

89

SRI(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

90

SRI(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

91

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

92

SRI(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

93

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

94

SRI(DP_SEC_TIMESTAMP, DP, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

98

SRI(AFMT_CNTL, DIG, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

103

SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

104

SRI(DCFE_MEM_PWR_STATUS, CRTC, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

108

SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

109

SRI(DCFE_MEM_PWR_STATUS, DCFE, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

113

SRI(DATA_FORMAT, LB, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

114

SRI(GAMUT_REMAP_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

115

SRI(GAMUT_REMAP_C11_C12, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

116

SRI(GAMUT_REMAP_C13_C14, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

117

SRI(GAMUT_REMAP_C21_C22, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

118

SRI(GAMUT_REMAP_C23_C24, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

119

SRI(GAMUT_REMAP_C31_C32, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

120

SRI(GAMUT_REMAP_C33_C34, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

121

SRI(OUTPUT_CSC_C11_C12, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

122

SRI(OUTPUT_CSC_C13_C14, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

123

SRI(OUTPUT_CSC_C21_C22, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

124

SRI(OUTPUT_CSC_C23_C24, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

125

SRI(OUTPUT_CSC_C31_C32, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

126

SRI(OUTPUT_CSC_C33_C34, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

127

SRI(OUTPUT_CSC_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

128

SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

129

SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

130

SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

131

SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

132

SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

133

SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

134

SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

135

SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

136

SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

137

SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

138

SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

139

SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

140

SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

141

SRI(REGAMMA_LUT_INDEX, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

142

SRI(REGAMMA_LUT_DATA, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

143

SRI(REGAMMA_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

144

SRI(DENORM_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

145

SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

146

SRI(OUT_ROUND_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

147

SRI(SCL_TAP_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

148

SRI(SCL_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

149

SRI(SCL_BYPASS_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

150

SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

151

SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

152

SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

153

SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

154

SRI(SCL_COEF_RAM_SELECT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

155

SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

156

SRI(VIEWPORT_START, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

157

SRI(VIEWPORT_SIZE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

158

SRI(SCL_SCALER_ENABLE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

159

SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

160

SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

161

SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

162

SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

163

SRI(SCL_VERT_FILTER_INIT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

164

SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

165

SRI(DC_LB_MEMORY_SPLIT, LB, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

166

SRI(DC_LB_MEM_SIZE, LB, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

167

SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

168

SRI(SCL_UPDATE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

169

SRI(SCL_F_SHARP_CONTROL, SCL, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

173

SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

39

SRI(LB_DATA_FORMAT, LB, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

40

SRI(GAMUT_REMAP_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

41

SRI(GAMUT_REMAP_C11_C12, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

42

SRI(GAMUT_REMAP_C13_C14, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

43

SRI(GAMUT_REMAP_C21_C22, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

44

SRI(GAMUT_REMAP_C23_C24, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

45

SRI(GAMUT_REMAP_C31_C32, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

46

SRI(GAMUT_REMAP_C33_C34, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

47

SRI(OUTPUT_CSC_C11_C12, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

48

SRI(OUTPUT_CSC_C13_C14, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

49

SRI(OUTPUT_CSC_C21_C22, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

50

SRI(OUTPUT_CSC_C23_C24, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

51

SRI(OUTPUT_CSC_C31_C32, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

52

SRI(OUTPUT_CSC_C33_C34, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

53

SRI(OUTPUT_CSC_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

54

SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

55

SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

56

SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

57

SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

58

SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

59

SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

60

SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

61

SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

62

SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

63

SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

64

SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

65

SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

66

SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

67

SRI(REGAMMA_LUT_INDEX, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

68

SRI(REGAMMA_LUT_DATA, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

69

SRI(REGAMMA_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

70

SRI(DENORM_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

71

SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

72

SRI(OUT_ROUND_CONTROL, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

73

SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

74

SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

75

SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

76

SRI(SCL_MODE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

77

SRI(SCL_TAP_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

78

SRI(SCL_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

79

SRI(SCL_BYPASS_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

80

SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

81

SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

82

SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

83

SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

84

SRI(SCL_COEF_RAM_SELECT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

85

SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

86

SRI(VIEWPORT_START, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

87

SRI(VIEWPORT_SIZE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

88

SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

89

SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

90

SRI(SCL_HORZ_FILTER_INIT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

91

SRI(SCL_VERT_FILTER_INIT, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

92

SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

93

SRI(LB_MEMORY_CTRL, LB, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

94

SRI(SCL_UPDATE, SCL, id), \

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

95

SRI(SCL_F_SHARP_CONTROL, SCL, id)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

99

SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

52

SRI(WB_ENABLE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

53

SRI(WB_EC_CONFIG, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

54

SRI(CNV_MODE, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

55

SRI(WB_SOFT_RESET, CNV, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

56

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

57

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

58

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

59

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

60

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

61

SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

62

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

63

SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

64

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

65

SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

66

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

67

SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

68

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

69

SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

70

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

71

SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

72

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

73

SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

74

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

75

SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

76

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

77

SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

78

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

79

SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

80

SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

81

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

82

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

35

SRI(FORMAT_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

36

SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

37

SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

38

SRI(CURSOR0_COLOR0, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

39

SRI(CURSOR0_COLOR1, CNVC_CUR, id)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

43

SRI(CURSOR_SETTINS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

44

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

45

SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

46

SRI(CURSOR_SIZE, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

47

SRI(CURSOR_CONTROL, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

48

SRI(CURSOR_POSITION, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

49

SRI(CURSOR_HOT_SPOT, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

50

SRI(CURSOR_DST_OFFSET, CURSOR, id)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

54

SRI(CURSOR_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

55

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

56

SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

57

SRI(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

58

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

59

SRI(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

60

SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

61

SRI(CURSOR_DST_OFFSET, CURSOR0_, id)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

65

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

66

SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

67

SRI(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

68

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

69

SRI(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

70

SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

71

SRI(CURSOR_DST_OFFSET, CURSOR0_, id)

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

32

SRI(CNTL, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

33

SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

34

SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

35

SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

36

SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

37

SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

38

SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

39

SRI(FMT_422_CONTROL, FMT, id)

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

72

SRI(RDPCSTX_PHY_CNTL15, RDPCSTX, id),\

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

73

SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

81

SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

82

SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

34

SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

35

SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

36

SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

37

SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

38

SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

39

SRI(AFMT_60958_0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

40

SRI(AFMT_60958_1, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

41

SRI(AFMT_60958_2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

42

SRI(AFMT_MEM_PWR, AFMT, id)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

35

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

36

SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

37

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

38

SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

39

SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

40

SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

41

SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

42

SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

43

SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

44

SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

45

SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

46

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

47

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

48

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

49

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

50

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

51

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

52

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

53

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

54

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

55

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

56

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

58

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

60

SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

61

SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

62

SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

63

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

64

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

65

SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

66

SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

67

SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

68

SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

69

SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

70

SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

71

SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

72

SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

73

SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

74

SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

75

SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

76

SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

83

SRI(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB, inst)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_opp.h

34

SRI(FMT_422_CONTROL, FMT, id)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

35

SRI(VPG_GENERIC_STATUS, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

36

SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

37

SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

38

SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

39

SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

34

SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

35

SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

36

SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

37

SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

38

SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

39

SRI(AFMT_60958_0, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

40

SRI(AFMT_60958_1, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

41

SRI(AFMT_60958_2, AFMT, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

42

SRI(AFMT_MEM_PWR, AFMT, id)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

34

SRI(APG_CONTROL, APG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

35

SRI(APG_CONTROL2, APG, id),\

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

36

SRI(APG_MEM_PWR, APG, id),\

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

37

SRI(APG_DBG_GEN_CONTROL, APG, id)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

35

SRI(VPG_GENERIC_STATUS, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

36

SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

37

SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

38

SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

39

SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

40

SRI(VPG_MEM_PWR, VPG, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

35

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

36

SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

37

SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

40

SRI(DC_HPD_CONTROL, HPD, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

43

SRI(DIG_BE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

44

SRI(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

45

SRI(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

46

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

47

SRI(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

48

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

49

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

50

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

51

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

52

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

53

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

54

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

55

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

56

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

57

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

58

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

59

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

60

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

61

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

62

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

63

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

64

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

65

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

66

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

70

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

35

SRI(AFMT_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

36

SRI(AFMT_GENERIC_0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

37

SRI(AFMT_GENERIC_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

38

SRI(AFMT_GENERIC_2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

39

SRI(AFMT_GENERIC_3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

40

SRI(AFMT_GENERIC_4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

41

SRI(AFMT_GENERIC_5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

42

SRI(AFMT_GENERIC_6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

43

SRI(AFMT_GENERIC_7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

44

SRI(AFMT_GENERIC_HDR, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

45

SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

46

SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

47

SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

48

SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

49

SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

50

SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

51

SRI(AFMT_60958_0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

52

SRI(AFMT_60958_1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

53

SRI(AFMT_60958_2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

54

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

55

SRI(DIG_FIFO_STATUS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

56

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

57

SRI(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

58

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

59

SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

60

SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

61

SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

62

SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

63

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

64

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

65

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

66

SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

67

SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

68

SRI(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

69

SRI(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

70

SRI(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

71

SRI(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

72

SRI(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

73

SRI(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

74

SRI(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

75

SRI(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

76

SRI(DP_MSA_VBID_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

77

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

78

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

79

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

80

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

81

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

82

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

83

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

84

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

85

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

86

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

87

SRI(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

88

SRI(DP_SEC_CNTL5, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

89

SRI(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

90

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

91

SRI(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

92

SRI(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

93

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

94

SRI(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

95

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

96

SRI(DP_SEC_AUD_N_READBACK, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

97

SRI(DP_SEC_AUD_M_READBACK, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

98

SRI(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

99

SRI(DIG_CLOCK_PATTERN, DIG, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

203

SRI(CLOCK_ENABLE, SYMCLK, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

204

SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

207

SRI(DIG_LANE_ENABLE, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

208

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

209

SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

210

SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

211

SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

212

SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

213

SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

214

SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

215

SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

216

SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

217

SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

218

SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

219

SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

220

SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

221

SRI(RDPCSTX_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

222

SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

223

SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

224

SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

225

SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

226

SRI(RDPCSTX_PLL_UPDATE_DATA, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

227

SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

228

SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

229

SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

230

SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

231

SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

232

SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

233

SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

234

SRI(DPCSTX_TX_CNTL, DPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

235

SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

236

SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

242

SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

243

SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

33

SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

35

SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

36

SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

37

SRI(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

38

SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

39

SRI(DME_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

40

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

41

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

42

SRI(DP_SEC_FRAMING4, DP, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

32

SRI(DIG_BE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

33

SRI(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

34

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

35

SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

36

SRI(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

37

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

38

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

39

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

40

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

41

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

42

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

43

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

44

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

45

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

46

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

47

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

48

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

49

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

50

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

51

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

52

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

53

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

54

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

55

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

100

SRI(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

101

SRI(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

102

SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

103

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

104

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

105

SRI(DP_SEC_FRAMING4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

106

SRI(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

107

SRI(DME_CONTROL, DME, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

108

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

109

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

110

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

111

SRI(DIG_FIFO_STATUS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

112

SRI(DIG_CLOCK_PATTERN, DIG, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

49

SRI(AFMT_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

50

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

51

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

52

SRI(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

53

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

54

SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

55

SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

56

SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

57

SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

58

SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

59

SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

60

SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

61

SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

62

SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

63

SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

64

SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

65

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

66

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

67

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

68

SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

69

SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

70

SRI(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

71

SRI(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

72

SRI(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

73

SRI(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

74

SRI(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

75

SRI(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

76

SRI(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

77

SRI(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

78

SRI(DP_MSA_VBID_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

79

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

80

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

81

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

82

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

83

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

84

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

85

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

86

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

87

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

88

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

89

SRI(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

90

SRI(DP_SEC_CNTL5, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

91

SRI(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

92

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

93

SRI(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

94

SRI(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

95

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

96

SRI(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

97

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

98

SRI(DP_SEC_AUD_N_READBACK, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

99

SRI(DP_SEC_AUD_M_READBACK, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

33

SRI(DIG_BE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

34

SRI(DIG_BE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

35

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

36

SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

37

SRI(DP_CONFIG, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

38

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

39

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

40

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

41

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

42

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

43

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

44

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

45

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

46

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

47

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

48

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

49

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

50

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

51

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

52

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

53

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

54

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

55

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

56

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

203

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

204

SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

205

SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

206

SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

207

SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

208

SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

209

SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

210

SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

211

SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

212

SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

213

SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

214

SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

215

SRI(RDPCSTX_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

216

SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

217

SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

218

SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

219

SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

220

SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

221

SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

222

SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

223

SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

224

SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

225

SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

226

SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

228

SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

229

SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

34

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

67

SRI(TMDS_CTL_BITS, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

68

SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

69

SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

70

SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

71

SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

72

SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

73

SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

74

SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

75

SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

76

SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

77

SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

78

SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

79

SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

80

SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

81

SRI(RDPCSTX_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

82

SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

83

SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

84

SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

85

SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

86

SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

87

SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

88

SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

89

SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

90

SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

91

SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

92

SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

94

SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

95

SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

100

SRI(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

101

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

102

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

103

SRI(DP_SEC_FRAMING4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

104

SRI(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

105

SRI(DME_CONTROL, DME, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

106

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

107

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

108

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

109

SRI(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

110

SRI(DIG_FIFO_CTRL0, DIG, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

50

SRI(AFMT_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

51

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

52

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

53

SRI(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

54

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

55

SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

56

SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

57

SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

58

SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

59

SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

60

SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

61

SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

62

SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

63

SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

64

SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

65

SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

66

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

67

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

68

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

69

SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

70

SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

71

SRI(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

72

SRI(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

73

SRI(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

74

SRI(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

75

SRI(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

76

SRI(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

77

SRI(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

78

SRI(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

79

SRI(DP_MSA_VBID_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

80

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

81

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

82

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

83

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

84

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

85

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

86

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

87

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

88

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

89

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

90

SRI(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

91

SRI(DP_SEC_CNTL5, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

92

SRI(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

93

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

94

SRI(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

95

SRI(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

96

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

97

SRI(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

98

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

99

SRI(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

100

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

101

SRI(DP_SEC_FRAMING4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

102

SRI(DP_GSP11_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

103

SRI(DME_CONTROL, DME, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

104

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

105

SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

106

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

107

SRI(DIG_FE_EN_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

108

SRI(DIG_FE_CLK_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

109

SRI(DIG_CLOCK_PATTERN, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

110

SRI(DIG_FIFO_CTRL0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

111

SRI(STREAM_MAPPER_CONTROL, DIG, id)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

48

SRI(AFMT_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

49

SRI(DIG_FE_CNTL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

50

SRI(HDMI_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

51

SRI(HDMI_DB_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

52

SRI(HDMI_GC, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

53

SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

54

SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

55

SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

56

SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

57

SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

58

SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

59

SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

60

SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

61

SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

62

SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

63

SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

64

SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

65

SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

66

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

67

SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

68

SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

69

SRI(HDMI_ACR_32_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

70

SRI(HDMI_ACR_32_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

71

SRI(HDMI_ACR_44_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

72

SRI(HDMI_ACR_44_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

73

SRI(HDMI_ACR_48_0, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

74

SRI(HDMI_ACR_48_1, DIG, id),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

75

SRI(DP_DB_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

76

SRI(DP_MSA_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

77

SRI(DP_MSA_VBID_MISC, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

78

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

79

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

80

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

81

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

82

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

83

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

84

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

85

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

86

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

87

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

88

SRI(DP_SEC_CNTL2, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

89

SRI(DP_SEC_CNTL5, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

90

SRI(DP_SEC_CNTL6, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

91

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

92

SRI(DP_VID_M, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

93

SRI(DP_VID_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

94

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

95

SRI(DP_VID_TIMING, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

96

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

97

SRI(DP_SEC_TIMESTAMP, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

98

SRI(DP_DSC_CNTL, DP, id), \

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

99

SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

100

SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

101

SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

102

SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

103

SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

104

SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

105

SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

106

SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

107

SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

108

SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

109

SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

110

SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

111

SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

112

SRI(CM_MEM_PWR_CTRL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

113

SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

114

SRI(CM_DGAM_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

115

SRI(CM_DGAM_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

116

SRI(CM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

117

SRI(CM_DGAM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

118

SRI(CM_TEST_DEBUG_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

119

SRI(CM_TEST_DEBUG_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

120

SRI(FORMAT_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

121

SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

122

SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

123

SRI(CURSOR0_COLOR0, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

124

SRI(CURSOR0_COLOR1, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

125

SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

126

SRI(DPP_CONTROL, DPP_TOP, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

127

SRI(CM_HDR_MULT_COEF, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

133

SRI(CM_COMA_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

134

SRI(CM_COMA_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

135

SRI(CM_COMB_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

136

SRI(CM_COMB_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

137

SRI(CM_OCSC_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

138

SRI(CM_OCSC_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

139

SRI(CM_OCSC_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

140

SRI(CM_BNS_VALUES_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

141

SRI(CM_BNS_VALUES_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

142

SRI(CM_BNS_VALUES_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

143

SRI(CM_MEM_PWR_CTRL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

144

SRI(CM_RGAM_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

145

SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

146

SRI(CM_RGAM_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

147

SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

148

SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

149

SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

150

SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

151

SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

152

SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

153

SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

154

SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

155

SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

156

SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

157

SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

158

SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

159

SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

160

SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

161

SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

162

SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

163

SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

164

SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

165

SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

166

SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

167

SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

168

SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

169

SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

170

SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

171

SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

172

SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

173

SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

174

SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

175

SRI(CM_RGAM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

176

SRI(CM_IGAM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

177

SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

178

SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

179

SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

180

SRI(CURSOR_CONTROL, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

181

SRI(CM_CMOUT_CONTROL, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

45

SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

46

SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

47

SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

48

SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

49

SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

50

SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

51

SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

52

SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

53

SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

54

SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

55

SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

56

SRI(OTG_H_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

57

SRI(OTG_V_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

58

SRI(SCL_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

59

SRI(LB_DATA_FORMAT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

60

SRI(LB_MEMORY_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

61

SRI(DSCL_AUTOCAL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

62

SRI(DSCL_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

63

SRI(SCL_BLACK_OFFSET, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

64

SRI(SCL_TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

65

SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

66

SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

67

SRI(DSCL_2TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

68

SRI(MPC_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

69

SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

70

SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

71

SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

72

SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

73

SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

74

SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

75

SRI(SCL_VERT_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

76

SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

77

SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

78

SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

79

SRI(RECOUT_START, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

80

SRI(RECOUT_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

81

SRI(CM_ICSC_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

82

SRI(CM_ICSC_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

83

SRI(CM_ICSC_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

84

SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

85

SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

86

SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

87

SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

88

SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

89

SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

90

SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

91

SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

92

SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

93

SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

94

SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

95

SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

96

SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

97

SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

98

SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

99

SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

100

SRI(CM_3DLUT_DATA_30BIT, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

101

SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

102

SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

103

SRI(CM_SHAPER_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

104

SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

105

SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

106

SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

107

SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

108

SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

109

SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

110

SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

111

SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

112

SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

113

SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

114

SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

115

SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

116

SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

117

SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

118

SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

119

SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

120

SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

121

SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

122

SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

123

SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

124

SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

125

SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

126

SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

127

SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

128

SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

129

SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

130

SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

131

SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

132

SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

133

SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

134

SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

135

SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

136

SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

137

SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

138

SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

139

SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

140

SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

141

SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

142

SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

143

SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

144

SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

145

SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

146

SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

147

SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

148

SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

149

SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

150

SRI(CM_SHAPER_LUT_INDEX, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

153

SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

154

SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

155

SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

156

SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

157

SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

158

SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

159

SRI(CM_ICSC_B_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

160

SRI(CM_ICSC_B_C33_C34, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

166

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

167

SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

168

SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

169

SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

170

SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

171

SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

172

SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

173

SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

174

SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

175

SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

176

SRI(COLOR_KEYER_RED, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

177

SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

178

SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

179

SRI(CM_SHAPER_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

180

SRI(CURSOR_CONTROL, CURSOR0_, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

181

SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

182

SRI(DSCL_MEM_PWR_CTRL, DSCL, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

33

SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

34

SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

35

SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

36

SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

37

SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

38

SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

39

SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

42

SRI(CM_BLNDGAM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

43

SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

44

SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

45

SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

46

SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

47

SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

48

SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

49

SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

50

SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

51

SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

52

SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

53

SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

54

SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

55

SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

56

SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

57

SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

58

SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

59

SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

60

SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

61

SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

62

SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

63

SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

64

SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

65

SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

66

SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

67

SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

68

SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

69

SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

70

SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

71

SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

72

SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

73

SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

74

SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

75

SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

76

SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

77

SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

78

SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

79

SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

80

SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

81

SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

82

SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

83

SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

84

SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

85

SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

86

SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

87

SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

88

SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

89

SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

90

SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

91

SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

92

SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

93

SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

94

SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

95

SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

96

SRI(CM_BLNDGAM_LUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

97

SRI(CM_3DLUT_MODE, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

98

SRI(CM_3DLUT_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

99

SRI(CM_3DLUT_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

100

SRI(OTG_V_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

101

SRI(SCL_MODE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

102

SRI(LB_DATA_FORMAT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

103

SRI(LB_MEMORY_CTRL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

104

SRI(DSCL_AUTOCAL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

105

SRI(DSCL_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

106

SRI(SCL_TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

107

SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

108

SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

109

SRI(DSCL_2TAP_CONTROL, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

110

SRI(MPC_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

111

SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

112

SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

113

SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

114

SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

115

SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

116

SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

117

SRI(SCL_VERT_FILTER_INIT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

118

SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

119

SRI(RECOUT_START, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

120

SRI(RECOUT_SIZE, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

121

SRI(PRE_DEALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

122

SRI(PRE_REALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

123

SRI(PRE_CSC_MODE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

124

SRI(PRE_CSC_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

125

SRI(PRE_CSC_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

126

SRI(PRE_CSC_B_C11_C12, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

127

SRI(PRE_CSC_B_C33_C34, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

128

SRI(CM_POST_CSC_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

129

SRI(CM_POST_CSC_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

130

SRI(CM_POST_CSC_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

131

SRI(CM_POST_CSC_B_C11_C12, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

132

SRI(CM_POST_CSC_B_C33_C34, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

133

SRI(CM_MEM_PWR_CTRL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

134

SRI(CM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

135

SRI(CM_TEST_DEBUG_INDEX, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

136

SRI(CM_TEST_DEBUG_DATA, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

137

SRI(FORMAT_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

138

SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

139

SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

140

SRI(CURSOR0_COLOR0, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

141

SRI(CURSOR0_COLOR1, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

142

SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

143

SRI(DPP_CONTROL, DPP_TOP, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

144

SRI(CM_HDR_MULT_COEF, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

145

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

146

SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

147

SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

148

SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

149

SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

150

SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

151

SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

152

SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

153

SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

154

SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

155

SRI(COLOR_KEYER_RED, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

156

SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

157

SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

158

SRI(CURSOR_CONTROL, CURSOR0_, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

159

SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

160

SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

161

SRI(DSCL_MEM_PWR_CTRL, DSCL, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

166

SRI(CM_BLNDGAM_CONTROL, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

167

SRI(CM_SHAPER_LUT_DATA, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

168

SRI(CM_MEM_PWR_CTRL2, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

169

SRI(CM_MEM_PWR_STATUS2, CM, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

170

SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

171

SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

172

SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

173

SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

174

SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

175

SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

176

SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

34

SRI(CM_DEALPHA, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

35

SRI(CM_MEM_PWR_STATUS, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

36

SRI(CM_BIAS_CR_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

37

SRI(CM_BIAS_Y_G_CB_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

38

SRI(PRE_DEGAM, CNVC_CFG, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

39

SRI(CM_GAMCOR_CONTROL, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

40

SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

41

SRI(CM_GAMCOR_LUT_INDEX, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

42

SRI(CM_GAMCOR_LUT_INDEX, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

43

SRI(CM_GAMCOR_LUT_DATA, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

44

SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

45

SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

46

SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

47

SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

48

SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

49

SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

50

SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

51

SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

52

SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

53

SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

54

SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

55

SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

56

SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

57

SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

58

SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

59

SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

60

SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

61

SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

62

SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

63

SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

64

SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

65

SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

66

SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

67

SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

68

SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

69

SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

70

SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

71

SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

72

SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

73

SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

74

SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

75

SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

76

SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

77

SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

78

SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

79

SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

80

SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

81

SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

82

SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

83

SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

84

SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

85

SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

86

SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

87

SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

88

SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

89

SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

90

SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

91

SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

92

SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

93

SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

94

SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

95

SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

96

SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

97

SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

98

SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

99

SRI(OTG_H_BLANK, DSCL, id), \

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

35

SRI(DSC_TOP_CONTROL, DSC_TOP, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

36

SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

37

SRI(DSCC_CONFIG0, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

38

SRI(DSCC_CONFIG1, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

39

SRI(DSCC_STATUS, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

40

SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

41

SRI(DSCC_PPS_CONFIG0, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

42

SRI(DSCC_PPS_CONFIG1, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

43

SRI(DSCC_PPS_CONFIG2, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

44

SRI(DSCC_PPS_CONFIG3, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

45

SRI(DSCC_PPS_CONFIG4, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

46

SRI(DSCC_PPS_CONFIG5, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

47

SRI(DSCC_PPS_CONFIG6, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

48

SRI(DSCC_PPS_CONFIG7, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

49

SRI(DSCC_PPS_CONFIG8, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

50

SRI(DSCC_PPS_CONFIG9, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

51

SRI(DSCC_PPS_CONFIG10, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

52

SRI(DSCC_PPS_CONFIG11, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

53

SRI(DSCC_PPS_CONFIG12, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

54

SRI(DSCC_PPS_CONFIG13, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

55

SRI(DSCC_PPS_CONFIG14, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

56

SRI(DSCC_PPS_CONFIG15, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

57

SRI(DSCC_PPS_CONFIG16, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

58

SRI(DSCC_PPS_CONFIG17, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

59

SRI(DSCC_PPS_CONFIG18, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

60

SRI(DSCC_PPS_CONFIG19, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

61

SRI(DSCC_PPS_CONFIG20, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

62

SRI(DSCC_PPS_CONFIG21, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

63

SRI(DSCC_PPS_CONFIG22, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

64

SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

65

SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

66

SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

67

SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

68

SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

69

SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

70

SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

71

SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

72

SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

73

SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

74

SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

75

SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

76

SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

77

SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

78

SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

79

SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

80

SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

81

SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

82

SRI(DSCCIF_CONFIG0, DSCCIF, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

83

SRI(DSCCIF_CONFIG1, DSCCIF, id),\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

84

SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

37

SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

38

SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

39

SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

40

SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

41

SRI(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

42

SRI(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

43

SRI(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

44

SRI(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

45

SRI(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

46

SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

47

SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

48

SRI(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

49

SRI(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

50

SRI(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

51

SRI(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

52

SRI(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

53

SRI(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

54

SRI(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

55

SRI(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

56

SRI(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

57

SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

58

SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

59

SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

60

SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

61

SRI(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

62

SRI(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

63

SRI(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

64

SRI(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

65

SRI(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

54

SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

55

SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

56

SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

57

SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

58

SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

59

SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

60

SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

61

SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

62

SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

63

SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

64

SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

65

SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

66

SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

67

SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

68

SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

69

SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

70

SRI(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

71

SRI(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

72

SRI(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

73

SRI(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

74

SRI(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

75

SRI(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

76

SRI(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

77

SRI(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

78

SRI(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

79

SRI(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

80

SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

81

SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

82

SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

83

SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

84

SRI(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

100

SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

101

SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

102

SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

103

SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

104

SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

105

SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

106

SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

107

SRI(HUBP_CLK_CNTL, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

108

SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

112

SRI(NOM_PARAMETERS_0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

113

SRI(NOM_PARAMETERS_1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

114

SRI(NOM_PARAMETERS_2, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

115

SRI(NOM_PARAMETERS_3, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

116

SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

121

SRI(PREFETCH_SETTINS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

122

SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

123

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

124

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

125

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

126

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

127

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

128

SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

129

SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

130

SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

131

SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

132

SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

133

SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

134

SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

135

SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

136

SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

137

SRI(CURSOR_SETTINS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

138

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

139

SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

140

SRI(CURSOR_SIZE, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

141

SRI(CURSOR_CONTROL, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

142

SRI(CURSOR_POSITION, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

143

SRI(CURSOR_HOT_SPOT, CURSOR, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

144

SRI(CURSOR_DST_OFFSET, CURSOR, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

35

SRI(DCHUBP_CNTL, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

36

SRI(HUBPREQ_DEBUG_DB, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

37

SRI(HUBPREQ_DEBUG, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

38

SRI(DCSURF_ADDR_CONFIG, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

39

SRI(DCSURF_TILING_CONFIG, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

40

SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

41

SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

42

SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

43

SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

44

SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

45

SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

46

SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

47

SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

48

SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

49

SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

50

SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

51

SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

52

SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

53

SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

54

SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

55

SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

56

SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

57

SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

58

SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

59

SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

60

SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

61

SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

62

SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

63

SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

64

SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

65

SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

66

SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

67

SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

68

SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

69

SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

70

SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

71

SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

72

SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

73

SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

74

SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

75

SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

76

SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

77

SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

78

SRI(HUBPRET_CONTROL, HUBPRET, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

79

SRI(HUBPRET_READ_LINE_STATUS, HUBPRET, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

80

SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

81

SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

82

SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

83

SRI(BLANK_OFFSET_0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

84

SRI(BLANK_OFFSET_1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

85

SRI(DST_DIMENSIONS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

86

SRI(DST_AFTER_SCALER, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

87

SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

88

SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

89

SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

90

SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

91

SRI(NOM_PARAMETERS_4, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

92

SRI(NOM_PARAMETERS_5, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

93

SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

94

SRI(PER_LINE_DELIVERY, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

95

SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

96

SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

97

SRI(NOM_PARAMETERS_6, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

98

SRI(NOM_PARAMETERS_7, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

99

SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

37

SRI(PREFETCH_SETTINGS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

38

SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

39

SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

40

SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

41

SRI(CURSOR_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

42

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

43

SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

44

SRI(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

45

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

46

SRI(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

47

SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

48

SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

49

SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

50

SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

51

SRI(DMDATA_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

52

SRI(DMDATA_SW_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

53

SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

54

SRI(DMDATA_SW_DATA, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

55

SRI(DMDATA_STATUS, CURSOR0_, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

56

SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

57

SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

58

SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

59

SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

60

SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

61

SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

62

SRI(VMID_SETTINGS_0, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

37

SRI(PREFETCH_SETTINGS, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

38

SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

39

SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

40

SRI(CURSOR_SETTINGS, HUBPREQ, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

41

SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

42

SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

43

SRI(CURSOR_SIZE, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

44

SRI(CURSOR_CONTROL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

45

SRI(CURSOR_POSITION, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

46

SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

47

SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

48

SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

49

SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

50

SRI(DMDATA_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

51

SRI(DMDATA_SW_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

52

SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

53

SRI(DMDATA_SW_DATA, CURSOR0_, id), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

54

SRI(DMDATA_STATUS, CURSOR0_, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

55

SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

56

SRI(FLIP_PARAMETERS_2, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

37

SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

38

SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

39

SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

40

SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

41

SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

42

SRI(VBLANK_PARAMETERS_6, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

34

SRI(DCN_DMDATA_VM_CNTL, HUBPREQ, id)

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

104

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

112

.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

77

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

84

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

95

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

174

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

181

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

192

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

201

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

177

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

184

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

197

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

206

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

126

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

133

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

144

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

153

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

187

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

194

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

219

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

228

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

196

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

203

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

228

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

237

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

179

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

185

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

215

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

224

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

122

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

128

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

139

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

148

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

182

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

189

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

214

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

223

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

184

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

191

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

216

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

225

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

189

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

196

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

221

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

230

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

193

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

200

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

225

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

234

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

181

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

188

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

213

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

219

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

160

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

167

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

192

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

159

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

166

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

197

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

173

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

180

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

205

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

214

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

33

SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

34

SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

35

SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

36

SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

37

SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

38

SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

39

SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

40

SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

41

SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

42

SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

43

SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

44

SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

45

SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

46

SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

47

SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

48

SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

49

SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

50

SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

51

SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

52

SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

53

SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

54

SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

55

SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

56

SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

57

SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

58

SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

59

SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

60

SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

61

SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

62

SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

63

SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

64

SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

65

SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

66

SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

67

SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

68

SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

69

SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

70

SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

71

SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

72

SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

73

SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

74

SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

75

SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

76

SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

77

SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

78

SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

79

SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

80

SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

81

SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

82

SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

83

SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

84

SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

85

SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

86

SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

87

SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

88

SRI(SMU_WM_CONTROL, WBIF, inst)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

37

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

38

SRI(FMT_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

39

SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

40

SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

41

SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

42

SRI(FMT_CLAMP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

43

SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

44

SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

45

SRI(OPPBUF_CONTROL, OPPBUF, id),\

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

46

SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

47

SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

48

SRI(OPP_PIPE_CONTROL, OPP_PIPE, id)

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

37

SRI(DPG_CONTROL, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

38

SRI(DPG_DIMENSIONS, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

39

SRI(DPG_OFFSET_SEGMENT, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

40

SRI(DPG_COLOUR_B_CB, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

41

SRI(DPG_COLOUR_G_Y, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

42

SRI(DPG_COLOUR_R_CR, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

43

SRI(DPG_RAMP_CONTROL, DPG, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

44

SRI(DPG_STATUS, DPG, id)

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

49

SRI(FMT_422_CONTROL, FMT, id), \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

50

SRI(OPPBUF_CONTROL1, OPPBUF, id)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

101

SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

102

SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

103

SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

104

SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

35

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

36

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

37

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

38

SRI(OTG_BLANK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

39

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

40

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

41

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

42

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

43

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

44

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

45

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

46

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

47

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

48

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

49

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

50

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

51

SRI(OTG_INTERLACE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

52

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

53

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

54

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

55

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

56

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

57

SRI(OTG_V_TOTAL_MID, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

58

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

59

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

60

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

61

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

62

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

63

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

64

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

65

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

66

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

67

SRI(OTG_BLACK_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

68

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

74

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

75

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

76

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

77

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

78

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

79

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

80

SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

81

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

82

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

83

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

84

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

85

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

86

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

87

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

88

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

89

SRI(OTG_CRC1_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

90

SRI(OTG_CRC1_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

91

SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

92

SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

93

SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

94

SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

96

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

97

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

33

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

34

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

35

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

36

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

37

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

38

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

39

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

40

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

41

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

42

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

43

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

45

SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

46

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

47

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

33

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

34

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

35

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

36

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

37

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

38

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

39

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

40

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h

41

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

100

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

101

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

102

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

103

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

104

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

105

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

106

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

107

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

108

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

109

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

110

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

111

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

113

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

34

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

35

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

36

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

37

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

38

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

39

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

40

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

41

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

42

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

43

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

44

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

45

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

46

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

47

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

48

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

49

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

50

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

51

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

52

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

53

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

54

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

55

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

56

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

57

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

58

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

60

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

61

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

62

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

63

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

64

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

65

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

66

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

67

SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

68

SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

69

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

70

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

71

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

74

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

75

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

76

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

77

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

78

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

79

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

80

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

81

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

82

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

83

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

84

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

85

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

86

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

87

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

88

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

89

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

90

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

91

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

93

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

94

SRI(OTG_DRR_CONTROL, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

99

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

100

SRI(OTG_CRC_CNTL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

102

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

103

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

104

SRI(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

32

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

33

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

34

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

35

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

36

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

37

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

38

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

39

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

40

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

41

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

42

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

43

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

44

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

45

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

46

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

47

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

48

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

49

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

50

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

51

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

52

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

53

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

54

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

55

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

56

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

57

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

58

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

59

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

60

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

61

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

62

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

63

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

64

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

65

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

66

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

67

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

68

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

73

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

74

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

75

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

76

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

77

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

78

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

79

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

80

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

81

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

82

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

83

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

84

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

85

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

87

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

88

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

89

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

90

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

91

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

92

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

93

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

94

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

95

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

96

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

97

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

98

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

99

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

100

SRI(OPTC_MEMORY_CONFIG, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

101

SRI(OTG_DRR_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

102

SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

103

SRI(INTERRUPT_DEST, OTG, inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

33

SRI(OTG_VSTARTUP_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

34

SRI(OTG_VUPDATE_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

35

SRI(OTG_VREADY_PARAM, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

36

SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

37

SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

38

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

39

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

40

SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

41

SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

42

SRI(OTG_H_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

43

SRI(OTG_H_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

44

SRI(OTG_H_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

45

SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

46

SRI(OTG_H_TIMING_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

47

SRI(OTG_V_TOTAL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

48

SRI(OTG_V_BLANK_START_END, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

49

SRI(OTG_V_SYNC_A, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

50

SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

51

SRI(OTG_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

52

SRI(OTG_STEREO_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

53

SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

54

SRI(OTG_STEREO_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

55

SRI(OTG_V_TOTAL_MAX, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

56

SRI(OTG_V_TOTAL_MIN, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

57

SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

58

SRI(OTG_TRIGA_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

59

SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

60

SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

61

SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

62

SRI(OTG_STATUS, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

63

SRI(OTG_STATUS_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

64

SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

65

SRI(OTG_M_CONST_DTO0, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

66

SRI(OTG_M_CONST_DTO1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

67

SRI(OTG_CLOCK_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

68

SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

69

SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

70

SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

71

SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

72

SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

73

SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

74

SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

75

SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

76

SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

77

SRI(CONTROL, VTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

78

SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

79

SRI(OTG_GSL_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

80

SRI(OTG_CRC_CNTL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

81

SRI(OTG_CRC0_DATA_RG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

82

SRI(OTG_CRC0_DATA_B, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

83

SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

84

SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

85

SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

86

SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

88

SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

89

SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

90

SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

91

SRI(OTG_GSL_WINDOW_X, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

92

SRI(OTG_GSL_WINDOW_Y, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

93

SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

94

SRI(OTG_DSC_START_POSITION, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

95

SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

96

SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

97

SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

98

SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

99

SRI(OPTC_WIDTH_CONTROL, ODM, inst),\

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

259

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

255

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

318

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1208

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

371

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

357

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

847

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

801

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \