distrib/special/more/curses.h
62
*SO, *SR, *TA, *TE, *TI, *UC, *UE, *UP, *US, *VB, *VS,
sbin/scsi/libscsi.h
43
#define SCSIREQ_ERROR(SR) \
sbin/scsi/libscsi.h
44
(SR->senselen_used || /* Sent sense */ \
sbin/scsi/libscsi.h
45
SR->status || /* Host adapter status */ \
sbin/scsi/libscsi.h
46
SR->retsts || /* SCSI transfer status */ \
sbin/scsi/libscsi.h
47
SR->error) /* copy of errno */
sys/arch/mips64/include/cpustate.h
109
RESTORE_REG(t1, SR, frame, bo) ;\
sys/arch/mips64/include/cpustate.h
82
SAVE_REG(a1, SR, frame, bo) ;\
sys/arch/mips64/include/regnum.h
69
#define PS SR /* alias for SR */
sys/arch/powerpc/ddb/db_disasm.c
843
u_int SR;
sys/arch/powerpc/ddb/db_disasm.c
844
SR = extract_field(instr, 15, 3);
sys/arch/powerpc/ddb/db_disasm.c
845
snprintf(lbuf, sizeof (lbuf), "sr%d", SR);
sys/arch/powerpc64/powerpc64/db_disasm.c
843
u_int SR;
sys/arch/powerpc64/powerpc64/db_disasm.c
844
SR = extract_field(instr, 15, 3);
sys/arch/powerpc64/powerpc64/db_disasm.c
845
snprintf(lbuf, sizeof (lbuf), "sr%d", SR);
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
32
SR(DPPCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
37
SR(REFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
40
SR(DISPCLK_FREQ_CHANGE_CNTL)
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
39
SR(PHYASYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
40
SR(PHYBSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
41
SR(PHYCSYMCLK_CLOCK_CNTL)
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
32
SR(DPPCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
37
SR(REFCLK_CNTL)
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
33
SR(DPPCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
36
SR(REFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
37
SR(DISPCLK_FREQ_CHANGE_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
32
SR(DPPCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
38
SR(PHYASYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
39
SR(PHYBSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
40
SR(PHYCSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
41
SR(PHYDSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
42
SR(PHYESYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
43
SR(DPSTREAMCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
44
SR(HDMISTREAMCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
45
SR(SYMCLK32_SE_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
46
SR(SYMCLK32_LE_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
59
SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
60
SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
61
SR(DCCG_AUDIO_DTO_SOURCE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
62
SR(DENTIST_DISPCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
63
SR(DSCCLK0_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
64
SR(DSCCLK1_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
65
SR(DSCCLK2_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
66
SR(DSCCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
67
SR(DCCG_GATE_DISABLE_CNTL2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
68
SR(DCCG_GATE_DISABLE_CNTL3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
69
SR(HDMISTREAMCLK0_DTO_PARAM)
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
37
SR(DPPCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
43
SR(PHYASYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
44
SR(PHYBSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
45
SR(PHYCSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
46
SR(PHYDSYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
47
SR(PHYESYMCLK_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
48
SR(DPSTREAMCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
49
SR(HDMISTREAMCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
50
SR(SYMCLK32_SE_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
51
SR(SYMCLK32_LE_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
64
SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
65
SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
66
SR(DCCG_AUDIO_DTO_SOURCE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
67
SR(DENTIST_DISPCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
68
SR(DSCCLK0_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
69
SR(DSCCLK1_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
70
SR(DSCCLK2_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
71
SR(DSCCLK3_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
72
SR(DSCCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
73
SR(DCCG_GATE_DISABLE_CNTL2),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
74
SR(DCCG_GATE_DISABLE_CNTL3),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
75
SR(HDMISTREAMCLK0_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
76
SR(OTG_PIXEL_RATE_DIV),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
77
SR(DTBCLK_P_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
78
SR(DCCG_AUDIO_DTO_SOURCE)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
36
SR(DPPCLK_CTRL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
37
SR(DCCG_GATE_DISABLE_CNTL4),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
38
SR(DCCG_GATE_DISABLE_CNTL5),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
39
SR(DCCG_GATE_DISABLE_CNTL6),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
40
SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
41
SR(SYMCLKA_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
42
SR(SYMCLKB_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
43
SR(SYMCLKC_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
44
SR(SYMCLKD_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
45
SR(SYMCLKE_CLOCK_ENABLE)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
33
SR(MASTER_COMM_CNTL_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
34
SR(MASTER_COMM_CMD_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
35
SR(MASTER_COMM_DATA_REG1)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
39
SR(DC_ABM1_HG_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
40
SR(DC_ABM1_LS_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
41
SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
42
SR(DC_ABM1_HG_MISC_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
43
SR(DC_ABM1_IPCSC_COEFF_SEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
44
SR(BL1_PWM_CURRENT_ABM_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
45
SR(BL1_PWM_TARGET_ABM_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
46
SR(BL1_PWM_USER_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
47
SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
48
SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
49
SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
50
SR(DC_ABM1_ACE_THRES_12), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
51
SR(BIOS_SCRATCH_2)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
71
SR(DC_ABM1_HG_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
72
SR(DC_ABM1_LS_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
73
SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
74
SR(DC_ABM1_HG_MISC_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
75
SR(DC_ABM1_IPCSC_COEFF_SEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
76
SR(BL1_PWM_CURRENT_ABM_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
77
SR(BL1_PWM_TARGET_ABM_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
78
SR(BL1_PWM_USER_LEVEL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
79
SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
80
SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
81
SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h
82
SR(DC_ABM1_ACE_THRES_12), \
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
33
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
34
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
35
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
36
SR(DCCG_AUDIO_DTO_SOURCE),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
37
SR(DCCG_AUDIO_DTO0_MODULE),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
38
SR(DCCG_AUDIO_DTO0_PHASE),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
39
SR(DCCG_AUDIO_DTO1_MODULE),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
40
SR(DCCG_AUDIO_DTO1_PHASE)
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
50
SR(AUXN_IMPCAL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
51
SR(AUXP_IMPCAL)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
33
SR(DMCU_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
34
SR(DMCU_STATUS), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
35
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
36
SR(DMCU_IRAM_WR_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
37
SR(DMCU_IRAM_WR_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
38
SR(MASTER_COMM_DATA_REG1), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
39
SR(MASTER_COMM_DATA_REG2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
40
SR(MASTER_COMM_DATA_REG3), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
41
SR(MASTER_COMM_CMD_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
42
SR(MASTER_COMM_CNTL_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
43
SR(SLAVE_COMM_DATA_REG1), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
44
SR(SLAVE_COMM_DATA_REG2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
45
SR(SLAVE_COMM_DATA_REG3), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
46
SR(SLAVE_COMM_CMD_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
47
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
48
SR(DMCU_IRAM_RD_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
49
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
50
SR(SMU_INTERRUPT_CONTROL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
51
SR(DC_DMCU_SCRATCH)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
55
SR(DMCU_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
56
SR(DMCU_STATUS), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
57
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
58
SR(DMCU_IRAM_WR_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
59
SR(DMCU_IRAM_WR_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
60
SR(MASTER_COMM_DATA_REG1), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
61
SR(MASTER_COMM_DATA_REG2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
62
SR(MASTER_COMM_DATA_REG3), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
63
SR(MASTER_COMM_CMD_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
64
SR(MASTER_COMM_CNTL_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
65
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
66
SR(DMCU_IRAM_RD_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
67
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
68
SR(DC_DMCU_SCRATCH)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
72
SR(DMCU_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
73
SR(DMCU_STATUS), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
74
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
75
SR(DMCU_IRAM_WR_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
76
SR(DMCU_IRAM_WR_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
77
SR(MASTER_COMM_DATA_REG1), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
78
SR(MASTER_COMM_DATA_REG2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
79
SR(MASTER_COMM_DATA_REG3), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
80
SR(MASTER_COMM_CMD_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
81
SR(MASTER_COMM_CNTL_REG), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
82
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
83
SR(DMCU_IRAM_RD_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
84
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
85
SR(SMU_INTERRUPT_CONTROL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
86
SR(DC_DMCU_SCRATCH)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
90
SR(DCI_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
94
SR(DMU_MEM_PWR_CNTL)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h
98
SR(DMCUB_SCRATCH15)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
100
SR(DIO_MEM_PWR_CTRL),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
101
SR(DIO_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
88
SR(DC_I2C_ARBITRATION),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
89
SR(DC_I2C_CONTROL),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
90
SR(DC_I2C_SW_STATUS),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
91
SR(DC_I2C_TRANSACTION0),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
92
SR(DC_I2C_TRANSACTION1),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
93
SR(DC_I2C_TRANSACTION2),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
94
SR(DC_I2C_TRANSACTION3),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
95
SR(DC_I2C_DATA),\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
96
SR(MICROSECOND_TIME_BASE_DIV)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
115
SR(DCI_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
122
SR(DCI_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
128
SR(DCI_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
48
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
49
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
50
SR(DMCU_IRAM_RD_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
51
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
77
SR(DCI_MEM_PWR_STATUS)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
82
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
83
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
84
SR(DMCU_IRAM_RD_DATA), \
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
85
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
104
SR(DCHUB_FB_LOCATION),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
105
SR(DCHUB_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
106
SR(DCHUB_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
107
SR(DCHUB_AGP_TOP)
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
39
SR(BL_PWM_CNTL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
40
SR(BL_PWM_CNTL2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
41
SR(BL_PWM_PERIOD_CNTL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
42
SR(BL_PWM_GRP1_REG_LOCK), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
43
SR(BIOS_SCRATCH_2)
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
53
SR(BL_PWM_CNTL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
54
SR(BL_PWM_CNTL2), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
55
SR(BL_PWM_PERIOD_CNTL), \
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h
56
SR(BL_PWM_GRP1_REG_LOCK), \
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
83
SR(RDPCSTX0_RDPCSTX_SCRATCH)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
237
SR(RDPCSTX0_RDPCSTX_SCRATCH)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
247
SR(DCIO_SOFT_RESET)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
227
SR(RDPCSTX0_RDPCSTX_SCRATCH), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
35
SR(DIO_LINKA_CNTL), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
36
SR(DIO_LINKB_CNTL), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
37
SR(DIO_LINKC_CNTL), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
38
SR(DIO_LINKD_CNTL), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
39
SR(DIO_LINKE_CNTL), \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
40
SR(DIO_LINKF_CNTL)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
93
SR(RDPCSTX0_RDPCSTX_SCRATCH), \
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
100
SR(DWB_OGAM_RAMA_REGION_28_29),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
101
SR(DWB_OGAM_RAMA_REGION_30_31),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
102
SR(DWB_OGAM_RAMA_REGION_32_33),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
103
SR(DWB_OGAM_RAMB_START_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
104
SR(DWB_OGAM_RAMB_START_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
105
SR(DWB_OGAM_RAMB_START_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
106
SR(DWB_OGAM_RAMB_START_BASE_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
107
SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
108
SR(DWB_OGAM_RAMB_START_BASE_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
109
SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
110
SR(DWB_OGAM_RAMB_START_BASE_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
111
SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
112
SR(DWB_OGAM_RAMB_END_CNTL1_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
113
SR(DWB_OGAM_RAMB_END_CNTL2_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
114
SR(DWB_OGAM_RAMB_END_CNTL1_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
115
SR(DWB_OGAM_RAMB_END_CNTL2_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
116
SR(DWB_OGAM_RAMB_END_CNTL1_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
117
SR(DWB_OGAM_RAMB_END_CNTL2_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
118
SR(DWB_OGAM_RAMB_OFFSET_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
119
SR(DWB_OGAM_RAMB_OFFSET_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
120
SR(DWB_OGAM_RAMB_OFFSET_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
121
SR(DWB_OGAM_RAMB_REGION_0_1),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
122
SR(DWB_OGAM_RAMB_REGION_2_3),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
123
SR(DWB_OGAM_RAMB_REGION_4_5),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
124
SR(DWB_OGAM_RAMB_REGION_6_7),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
125
SR(DWB_OGAM_RAMB_REGION_8_9),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
126
SR(DWB_OGAM_RAMB_REGION_10_11),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
127
SR(DWB_OGAM_RAMB_REGION_12_13),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
128
SR(DWB_OGAM_RAMB_REGION_14_15),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
129
SR(DWB_OGAM_RAMB_REGION_16_17),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
130
SR(DWB_OGAM_RAMB_REGION_18_19),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
131
SR(DWB_OGAM_RAMB_REGION_20_21),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
132
SR(DWB_OGAM_RAMB_REGION_22_23),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
133
SR(DWB_OGAM_RAMB_REGION_24_25),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
134
SR(DWB_OGAM_RAMB_REGION_26_27),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
135
SR(DWB_OGAM_RAMB_REGION_28_29),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
136
SR(DWB_OGAM_RAMB_REGION_30_31),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
137
SR(DWB_OGAM_RAMB_REGION_32_33)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
31
SR(DWB_ENABLE_CLK_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
32
SR(DWB_MEM_PWR_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
33
SR(FC_MODE_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
34
SR(FC_FLOW_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
35
SR(FC_WINDOW_START),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
36
SR(FC_WINDOW_SIZE),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
37
SR(FC_SOURCE_SIZE),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
38
SR(DWB_UPDATE_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
39
SR(DWB_CRC_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
40
SR(DWB_CRC_MASK_R_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
41
SR(DWB_CRC_MASK_B_A),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
42
SR(DWB_CRC_VAL_R_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
43
SR(DWB_CRC_VAL_B_A),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
44
SR(DWB_OUT_CTRL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
45
SR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
46
SR(DWB_MMHUBBUB_BACKPRESSURE_CNT),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
47
SR(DWB_HOST_READ_CONTROL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
48
SR(DWB_SOFT_RESET),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
49
SR(DWB_HDR_MULT_COEF),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
50
SR(DWB_GAMUT_REMAP_MODE),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
51
SR(DWB_GAMUT_REMAP_COEF_FORMAT),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
52
SR(DWB_GAMUT_REMAPA_C11_C12),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
53
SR(DWB_GAMUT_REMAPA_C13_C14),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
54
SR(DWB_GAMUT_REMAPA_C21_C22),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
55
SR(DWB_GAMUT_REMAPA_C23_C24),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
56
SR(DWB_GAMUT_REMAPA_C31_C32),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
57
SR(DWB_GAMUT_REMAPA_C33_C34),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
58
SR(DWB_GAMUT_REMAPB_C11_C12),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
59
SR(DWB_GAMUT_REMAPB_C13_C14),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
60
SR(DWB_GAMUT_REMAPB_C21_C22),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
61
SR(DWB_GAMUT_REMAPB_C23_C24),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
62
SR(DWB_GAMUT_REMAPB_C31_C32),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
63
SR(DWB_GAMUT_REMAPB_C33_C34),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
64
SR(DWB_OGAM_CONTROL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
65
SR(DWB_OGAM_LUT_INDEX),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
66
SR(DWB_OGAM_LUT_DATA),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
67
SR(DWB_OGAM_LUT_CONTROL),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
68
SR(DWB_OGAM_RAMA_START_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
69
SR(DWB_OGAM_RAMA_START_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
70
SR(DWB_OGAM_RAMA_START_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
71
SR(DWB_OGAM_RAMA_START_BASE_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
72
SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
73
SR(DWB_OGAM_RAMA_START_BASE_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
74
SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
75
SR(DWB_OGAM_RAMA_START_BASE_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
76
SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
77
SR(DWB_OGAM_RAMA_END_CNTL1_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
78
SR(DWB_OGAM_RAMA_END_CNTL2_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
79
SR(DWB_OGAM_RAMA_END_CNTL1_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
80
SR(DWB_OGAM_RAMA_END_CNTL2_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
81
SR(DWB_OGAM_RAMA_END_CNTL1_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
82
SR(DWB_OGAM_RAMA_END_CNTL2_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
83
SR(DWB_OGAM_RAMA_OFFSET_B),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
84
SR(DWB_OGAM_RAMA_OFFSET_G),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
85
SR(DWB_OGAM_RAMA_OFFSET_R),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
86
SR(DWB_OGAM_RAMA_REGION_0_1),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
87
SR(DWB_OGAM_RAMA_REGION_2_3),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
88
SR(DWB_OGAM_RAMA_REGION_4_5),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
89
SR(DWB_OGAM_RAMA_REGION_6_7),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
90
SR(DWB_OGAM_RAMA_REGION_8_9),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
91
SR(DWB_OGAM_RAMA_REGION_10_11),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
92
SR(DWB_OGAM_RAMA_REGION_12_13),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
93
SR(DWB_OGAM_RAMA_REGION_14_15),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
94
SR(DWB_OGAM_RAMA_REGION_16_17),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
95
SR(DWB_OGAM_RAMA_REGION_18_19),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
96
SR(DWB_OGAM_RAMA_REGION_20_21),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
97
SR(DWB_OGAM_RAMA_REGION_22_23),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
98
SR(DWB_OGAM_RAMA_REGION_24_25),\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
99
SR(DWB_OGAM_RAMA_REGION_26_27),\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
50
SR(DP_STREAM_MAPPER_CONTROL0),\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
51
SR(DP_STREAM_MAPPER_CONTROL1),\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
52
SR(DP_STREAM_MAPPER_CONTROL2),\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
53
SR(DP_STREAM_MAPPER_CONTROL3),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
36
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
37
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
38
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
39
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
40
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
41
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
42
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
43
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
44
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
45
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
46
SR(DCHUBBUB_ARB_SAT_LEVEL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
47
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
48
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
49
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
50
SR(DCHUBBUB_TEST_DEBUG_DATA),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
51
SR(DCHUBBUB_SOFT_RESET)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
54
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
55
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
56
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
57
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
60
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
61
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
62
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
63
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
64
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
65
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
66
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
67
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
73
SR(DCHUBBUB_SDPIF_FB_TOP),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
74
SR(DCHUBBUB_SDPIF_FB_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
75
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
76
SR(DCHUBBUB_SDPIF_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
77
SR(DCHUBBUB_SDPIF_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
78
SR(DCHUBBUB_SDPIF_AGP_TOP)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
37
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
38
SR(DCN_VM_FB_LOCATION_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
39
SR(DCN_VM_FB_LOCATION_TOP),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
40
SR(DCN_VM_FB_OFFSET),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
41
SR(DCN_VM_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
42
SR(DCN_VM_AGP_TOP),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
43
SR(DCN_VM_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
44
SR(DCN_VM_FAULT_ADDR_MSB), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
45
SR(DCN_VM_FAULT_ADDR_LSB), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
46
SR(DCN_VM_FAULT_CNTL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
47
SR(DCN_VM_FAULT_STATUS)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
53
SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
54
SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h
33
SR(DCHUBBUB_CRC_CTRL)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
31
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
32
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
33
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
34
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
35
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
36
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
37
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
38
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
39
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
40
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
41
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
42
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
43
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
44
SR(DCHVM_CTRL0), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
45
SR(DCHVM_MEM_CTRL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
46
SR(DCHVM_CLK_CTRL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
47
SR(DCHVM_RIOMMU_CTRL0), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
48
SR(DCHVM_RIOMMU_STAT0)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
40
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
41
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
42
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
43
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
44
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
45
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
46
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
47
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
48
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
49
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
50
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
51
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
33
SR(DCHVM_CTRL0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
34
SR(DCHVM_MEM_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
35
SR(DCHVM_CLK_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
36
SR(DCHVM_RIOMMU_CTRL0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
37
SR(DCHVM_RIOMMU_STAT0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
38
SR(DCHUBBUB_DET0_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
39
SR(DCHUBBUB_DET1_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
40
SR(DCHUBBUB_DET2_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
41
SR(DCHUBBUB_DET3_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
42
SR(DCHUBBUB_COMPBUF_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
43
SR(COMPBUF_RESERVED_SPACE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
44
SR(DCHUBBUB_DEBUG_CTRL_0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
45
SR(DCHUBBUB_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
46
SR(DCHUBBUB_SDPIF_CFG0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
47
SR(DCHUBBUB_SDPIF_CFG1),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
48
SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
49
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
50
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
51
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
52
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
53
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
54
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
55
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h
56
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
100
SR(DCHUBBUB_DEBUG_CTRL_0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
101
SR(DCHUBBUB_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
102
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
103
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
104
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
105
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
106
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
107
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
108
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
109
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
110
SR(DCHUBBUB_ARB_QOS_FORCE)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
33
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
34
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
35
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
36
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
37
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
38
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
39
SR(DCHUBBUB_ARB_SAT_LEVEL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
40
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
41
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
42
SR(DCHUBBUB_SOFT_RESET),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
43
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
44
SR(DCN_VM_FB_LOCATION_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
45
SR(DCN_VM_FB_LOCATION_TOP),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
46
SR(DCN_VM_FB_OFFSET),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
47
SR(DCN_VM_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
48
SR(DCN_VM_AGP_TOP),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
49
SR(DCN_VM_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
51
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
52
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
53
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
54
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
55
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
56
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
57
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
58
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
59
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
60
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
61
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
62
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
63
SR(DCHUBBUB_DET0_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
64
SR(DCHUBBUB_DET1_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
65
SR(DCHUBBUB_DET2_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
66
SR(DCHUBBUB_DET3_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
67
SR(DCHUBBUB_COMPBUF_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
68
SR(COMPBUF_RESERVED_SPACE),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
69
SR(DCHUBBUB_DEBUG_CTRL_0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
70
SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
71
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
72
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
73
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
74
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
75
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
76
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
77
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
78
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
79
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
80
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
81
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
82
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
83
SR(DCN_VM_FAULT_ADDR_MSB),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
84
SR(DCN_VM_FAULT_ADDR_LSB),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
85
SR(DCN_VM_FAULT_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
86
SR(DCN_VM_FAULT_STATUS),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
87
SR(SDPIF_REQUEST_RATE_LIMIT),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
88
SR(DCHUBBUB_CLOCK_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
89
SR(DCHUBBUB_SDPIF_CFG0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
90
SR(DCHUBBUB_SDPIF_CFG1),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
91
SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
92
SR(DCHUBBUB_ARB_HOSTVM_CNTL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
93
SR(DCHVM_CTRL0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
94
SR(DCHVM_MEM_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
95
SR(DCHVM_CLK_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
96
SR(DCHVM_RIOMMU_CTRL0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
97
SR(DCHVM_RIOMMU_STAT0),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
98
SR(DCHUBBUB_COMPBUF_CTRL),\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
99
SR(COMPBUF_RESERVED_SPACE),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
66
SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
67
SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
129
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
130
SR(DCFEV_CLOCK_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
139
SR(BLNDV_CONTROL),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
180
SR(DCHUB_FB_LOCATION),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
181
SR(DCHUB_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
182
SR(DCHUB_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
183
SR(DCHUB_AGP_TOP)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
195
SR(REFCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
196
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
197
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
198
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
199
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
200
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
201
SR(DCFCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
202
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
228
SR(DCHUBBUB_SDPIF_FB_BASE),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
229
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
230
SR(DCHUBBUB_SDPIF_AGP_BASE),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
231
SR(DCHUBBUB_SDPIF_AGP_BOT),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
232
SR(DCHUBBUB_SDPIF_AGP_TOP),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
233
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
234
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
235
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
236
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
237
SR(DOMAIN4_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
238
SR(DOMAIN5_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
239
SR(DOMAIN6_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
240
SR(DOMAIN7_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
241
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
242
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
243
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
244
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
245
SR(DOMAIN4_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
246
SR(DOMAIN5_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
247
SR(DOMAIN6_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
248
SR(DOMAIN7_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
249
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
250
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
251
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
252
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
253
SR(VGA_TEST_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
254
SR(DC_IP_REQUEST_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
264
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
265
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
266
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
267
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
268
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
269
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
270
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
271
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
272
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
273
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
274
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
275
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
276
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
277
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
278
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
279
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
280
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
281
SR(DOMAIN4_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
282
SR(DOMAIN5_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
283
SR(DOMAIN6_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
284
SR(DOMAIN7_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
285
SR(DOMAIN8_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
286
SR(DOMAIN9_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
289
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
290
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
291
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
292
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
293
SR(DOMAIN20_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
294
SR(DOMAIN21_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
295
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
296
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
297
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
298
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
299
SR(DOMAIN4_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
300
SR(DOMAIN5_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
301
SR(DOMAIN6_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
302
SR(DOMAIN7_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
303
SR(DOMAIN8_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
304
SR(DOMAIN9_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
305
SR(DOMAIN10_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
306
SR(DOMAIN11_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
307
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
308
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
309
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
310
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
311
SR(DOMAIN20_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
312
SR(DOMAIN21_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
313
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
314
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
315
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
316
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
317
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
318
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
319
SR(DC_IP_REQUEST_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
328
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
329
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
330
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
331
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
332
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
333
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
334
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
335
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
336
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
337
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
338
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
339
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
340
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
341
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
342
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
343
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
344
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
345
SR(DOMAIN4_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
346
SR(DOMAIN5_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
347
SR(DOMAIN6_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
348
SR(DOMAIN7_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
349
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
350
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
351
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
352
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
353
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
354
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
355
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
356
SR(DOMAIN4_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
357
SR(DOMAIN5_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
358
SR(DOMAIN6_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
359
SR(DOMAIN7_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
360
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
361
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
362
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
363
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
364
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
365
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
366
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
367
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
368
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
369
SR(DC_IP_REQUEST_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
375
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
376
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
377
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
378
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
379
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
380
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
381
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
382
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
383
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
384
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
385
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
386
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
387
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
388
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
389
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
399
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
400
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
401
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
402
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
403
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
404
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
405
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
406
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
407
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
408
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
409
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
410
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
411
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
412
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
413
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
414
SR(HPO_TOP_CLOCK_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
415
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
416
SR(DMU_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
417
SR(MMHUBBUB_MEM_PWR_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
420
SR(REFCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
421
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
422
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
423
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
424
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
425
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
426
SR(DCFCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
427
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
436
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
437
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
438
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
439
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
440
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
441
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
442
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
443
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
444
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
445
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
446
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
447
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
448
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
449
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
45
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
450
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
451
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
452
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
453
SR(DOMAIN4_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
454
SR(DOMAIN5_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
455
SR(DOMAIN6_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
456
SR(DOMAIN7_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
457
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
458
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
459
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
460
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
461
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
462
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
463
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
464
SR(DOMAIN4_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
465
SR(DOMAIN5_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
466
SR(DOMAIN6_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
467
SR(DOMAIN7_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
468
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
469
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
470
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
471
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
472
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
473
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
474
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
475
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
476
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
477
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
478
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
479
SR(AZALIA_CONTROLLER_CLOCK_GATING)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
488
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
489
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
490
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
491
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
492
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
493
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
494
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
495
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
496
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
497
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
498
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
499
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
500
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
501
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
502
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
503
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
504
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
505
SR(DOMAIN4_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
506
SR(DOMAIN5_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
507
SR(DOMAIN6_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
508
SR(DOMAIN7_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
509
SR(DOMAIN8_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
510
SR(DOMAIN9_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
511
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
512
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
513
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
514
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
515
SR(DOMAIN20_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
516
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
517
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
518
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
519
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
520
SR(DOMAIN4_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
521
SR(DOMAIN5_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
522
SR(DOMAIN6_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
523
SR(DOMAIN7_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
524
SR(DOMAIN8_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
525
SR(DOMAIN9_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
526
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
527
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
528
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
529
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
530
SR(DOMAIN20_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
531
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
532
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
533
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
534
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
535
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
536
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
537
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
540
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
541
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
542
SR(HPO_TOP_CLOCK_CONTROL)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
548
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
549
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
550
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
551
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
552
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
553
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
554
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
555
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
556
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
557
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
558
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
559
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
560
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
561
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
562
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
563
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
564
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
565
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
566
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
569
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
570
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
571
SR(HPO_TOP_CLOCK_CONTROL)
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
101
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
106
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
111
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
155
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
203
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
211
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
225
SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
94
SR(DENTIST_DISPCLK_CNTL)
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
98
SR(DENTIST_DISPCLK_CNTL)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
84
SR(MPC_OCSC_TEST_DEBUG_DATA),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
85
SR(MPC_OCSC_TEST_DEBUG_INDEX)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
112
SR(MPC_OUT_CSC_COEF_FORMAT)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
115
SR(MPC_RMU_CONTROL),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
116
SR(MPC_RMU_MEM_PWR_CTRL)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
95
SR(GSL_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
44
SR(DWB_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
42
SR(DWB_SOURCE_SELECT)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
112
SR(DWB_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
92
SR(GSL_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
101
SR(DWB_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
86
SR(GSL_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
87
SR(GSL_SOURCE_SELECT),\
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
33
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
34
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
35
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
36
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
37
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
38
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
39
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
40
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
41
SR(DOMAIN22_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
42
SR(DOMAIN23_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
43
SR(DOMAIN24_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
44
SR(DOMAIN25_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
45
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
46
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
47
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
48
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
49
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
50
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
51
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
52
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
53
SR(DOMAIN22_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
54
SR(DOMAIN23_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
55
SR(DOMAIN24_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
56
SR(DOMAIN25_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
57
SR(DC_IP_REQUEST_CNTL)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
679
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
680
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
681
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
682
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
683
SR(DMU_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
684
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
685
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
686
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
687
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
688
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
697
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
698
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
699
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
700
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
701
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
702
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
703
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
704
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
705
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
706
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
707
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
708
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
709
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
710
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
711
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
712
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
713
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
714
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
715
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
716
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
717
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
718
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
719
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
720
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
721
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
722
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
723
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
724
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
725
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
726
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
727
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
728
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
729
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
730
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
731
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
732
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
733
SR(HPO_TOP_HW_CONTROL)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
686
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
687
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
688
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
689
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
690
SR(DMU_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
691
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
692
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
693
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
694
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
695
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
704
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
705
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
706
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
707
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
708
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
709
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
710
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
711
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
712
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
713
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
714
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
715
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
716
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
717
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
718
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
719
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
720
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
721
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
722
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
723
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
724
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
725
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
726
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
727
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
728
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
729
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
730
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
731
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
732
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
733
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
734
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
735
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
736
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
737
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
738
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
739
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
740
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
741
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
742
SR(HPO_TOP_HW_CONTROL)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
678
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
679
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
680
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
681
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
682
SR(DMU_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
683
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
684
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
685
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
686
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
687
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
696
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
697
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
698
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
699
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
700
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
701
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
702
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
703
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
704
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
705
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
706
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
707
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
708
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
709
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
710
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
711
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
712
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
713
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
714
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
715
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
716
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
717
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
718
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
719
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
720
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
721
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
722
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
723
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
724
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
725
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
726
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
727
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
728
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
729
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
730
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
731
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
732
SR(HPO_TOP_HW_CONTROL)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
673
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
674
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
675
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
676
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
677
SR(DMU_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
678
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
679
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
680
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
681
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
682
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
691
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
692
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
693
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
694
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
695
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
696
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
697
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
698
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
699
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
700
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
701
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
702
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
703
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
704
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
705
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
706
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
707
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
708
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
709
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
710
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
711
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
712
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
713
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
714
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
715
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
716
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
717
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
718
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
719
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
720
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
721
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
722
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
723
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
724
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
725
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
726
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
727
SR(HPO_TOP_HW_CONTROL)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
532
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
533
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
534
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
535
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
536
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
537
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
538
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
539
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
548
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
549
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
550
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
551
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
552
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
553
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
554
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
555
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
556
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
557
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
558
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
559
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
560
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
561
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
562
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
563
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
564
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
565
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
566
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
567
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
568
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
569
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
570
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
571
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
572
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
573
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
574
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
575
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
576
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
577
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
578
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
579
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
580
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
581
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
582
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
583
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
584
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
585
SR(AZALIA_CONTROLLER_CLOCK_GATING)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1191
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1192
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1193
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1194
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1195
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1196
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1197
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1198
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1199
SR(DCHUBBUB_TEST_DEBUG_DATA), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1200
SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1201
SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1202
SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1203
SR(DCN_VM_AGP_BASE), HUBBUB_SR_WATERMARK_REG_LIST(), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1204
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1205
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1206
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1207
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1208
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1209
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1210
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1211
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1212
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1213
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D), SR(DCHUBBUB_DET0_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1214
SR(DCHUBBUB_DET1_CTRL), SR(DCHUBBUB_DET2_CTRL), SR(DCHUBBUB_DET3_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1215
SR(DCHUBBUB_COMPBUF_CTRL), SR(COMPBUF_RESERVED_SPACE), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1216
SR(DCHUBBUB_DEBUG_CTRL_0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1217
SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1218
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1219
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1220
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1221
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1222
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1223
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1224
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1225
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1226
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1227
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1228
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1229
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1230
SR(DCHUBBUB_ARB_MALL_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1231
SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1232
SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1233
SR(SDPIF_REQUEST_RATE_LIMIT), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1234
SR(DCHUBBUB_SDPIF_CFG0)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1239
SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1242
SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1243
SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1244
SR(PHYESYMCLK_CLOCK_CNTL), SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1245
SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1252
SR(DCCG_AUDIO_DTBCLK_DTO_MODULO), SR(DCCG_AUDIO_DTBCLK_DTO_PHASE), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1253
SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1254
SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
789
SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
528
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
529
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
530
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
531
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
532
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
533
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
534
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
535
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
544
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
545
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
546
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
547
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
548
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
549
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
550
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
551
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
552
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
553
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
554
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
555
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
556
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
557
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
558
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
559
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
560
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
561
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
562
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
563
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
564
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
565
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
566
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
567
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
568
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
569
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
570
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
571
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
572
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
573
SR(D1VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
574
SR(D2VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
575
SR(D3VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
576
SR(D4VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
577
SR(D5VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
578
SR(D6VGA_CONTROL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
579
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
580
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
581
SR(AZALIA_CONTROLLER_CLOCK_GATING)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
163
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
164
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
165
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
166
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
167
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
168
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
169
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
170
SR(DCCG_GATE_DISABLE_CNTL4), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
171
SR(DCCG_GATE_DISABLE_CNTL5), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
172
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
173
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
182
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
183
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
184
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
185
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
186
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
187
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
188
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
189
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
190
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
191
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
192
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
193
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
194
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
195
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
196
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
197
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
198
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
199
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
200
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
201
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
202
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
203
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
204
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
205
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
206
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
207
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
208
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
209
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
210
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
211
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
212
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
213
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
214
SR(HPO_TOP_HW_CONTROL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
215
SR(DMU_CLK_CNTL)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
24
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
25
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
26
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
27
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
28
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
29
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
30
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
31
SR(DCCG_GATE_DISABLE_CNTL4), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
32
SR(DCCG_GATE_DISABLE_CNTL5), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
33
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
34
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
43
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
44
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
45
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
46
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
47
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
48
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
49
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
50
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
51
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
52
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
53
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
54
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
55
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
56
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
57
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
58
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
59
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
60
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
61
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
62
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
63
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
64
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
65
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
66
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
67
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
68
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
69
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
70
SR(HPO_TOP_HW_CONTROL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
71
SR(DMU_CLK_CNTL)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
507
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
508
SR(DIO_MEM_PWR_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
509
SR(ODM_MEM_PWR_CTRL3), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
510
SR(MMHUBBUB_MEM_PWR_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
511
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
512
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
513
SR(DCFCLK_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
514
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
523
SR(MICROSECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
524
SR(MILLISECOND_TIME_BASE_DIV), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
525
SR(DISPCLK_FREQ_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
526
SR(RBBMIF_TIMEOUT_DIS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
527
SR(RBBMIF_TIMEOUT_DIS_2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
528
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
529
SR(DPP_TOP0_DPP_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
530
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
531
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
532
SR(MPC_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
533
SR(MPC_CRC_RESULT_GB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
534
SR(MPC_CRC_RESULT_C), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
535
SR(MPC_CRC_RESULT_AR), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
536
SR(DOMAIN0_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
537
SR(DOMAIN1_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
538
SR(DOMAIN2_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
539
SR(DOMAIN3_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
540
SR(DOMAIN16_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
541
SR(DOMAIN17_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
542
SR(DOMAIN18_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
543
SR(DOMAIN19_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
544
SR(DOMAIN22_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
545
SR(DOMAIN23_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
546
SR(DOMAIN24_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
547
SR(DOMAIN25_PG_CONFIG), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
548
SR(DOMAIN0_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
549
SR(DOMAIN1_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
550
SR(DOMAIN2_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
551
SR(DOMAIN3_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
552
SR(DOMAIN16_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
553
SR(DOMAIN17_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
554
SR(DOMAIN18_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
555
SR(DOMAIN19_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
556
SR(DOMAIN22_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
557
SR(DOMAIN23_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
558
SR(DOMAIN24_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
559
SR(DOMAIN25_PG_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
560
SR(DC_IP_REQUEST_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
561
SR(AZALIA_AUDIO_DTO), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
562
SR(HPO_TOP_HW_CONTROL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
563
SR(AZALIA_CONTROLLER_CLOCK_GATING)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
547
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
548
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
549
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
550
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
551
SR(DCHUBBUB_ARB_SAT_LEVEL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
552
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
553
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
554
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
555
SR(DCHUBBUB_TEST_DEBUG_DATA), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
556
SR(DCHUBBUB_SOFT_RESET), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
557
SR(DCHUBBUB_CRC_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
558
SR(DCN_VM_FB_LOCATION_BASE), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
559
SR(DCN_VM_FB_LOCATION_TOP), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
560
SR(DCN_VM_FB_OFFSET), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
561
SR(DCN_VM_AGP_BOT), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
562
SR(DCN_VM_AGP_TOP), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
563
SR(DCN_VM_AGP_BASE), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
564
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
565
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
566
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
567
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
568
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
569
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
570
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
571
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
572
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
573
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
574
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
575
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
576
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
577
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
578
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
579
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
580
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
581
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
582
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
583
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
584
SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
585
SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
586
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
587
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
588
SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
589
SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
590
SR(DCHUBBUB_DET0_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
591
SR(DCHUBBUB_DET1_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
592
SR(DCHUBBUB_DET2_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
593
SR(DCHUBBUB_DET3_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
594
SR(DCHUBBUB_COMPBUF_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
595
SR(COMPBUF_RESERVED_SPACE), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
596
SR(DCHUBBUB_DEBUG_CTRL_0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
597
SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
598
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
599
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
600
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
601
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
602
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
603
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
604
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
605
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
606
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
607
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
608
SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
609
SR(DCN_VM_FAULT_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
610
SR(DCN_VM_FAULT_STATUS), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
611
SR(SDPIF_REQUEST_RATE_LIMIT), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
612
SR(DCHUBBUB_CLOCK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
613
SR(DCHUBBUB_SDPIF_CFG0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
614
SR(DCHUBBUB_SDPIF_CFG1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
615
SR(DCHUBBUB_MEM_PWR_MODE_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
616
SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
617
SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
618
SR(DCHUBBUB_CTRL_STATUS)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
623
SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
626
SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
627
SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
628
SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
629
SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
632
SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
633
SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
634
SR(DPPCLK_CTRL), \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
639
SR(DSCCLK0_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
640
SR(DSCCLK1_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
641
SR(DSCCLK2_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
642
SR(DSCCLK3_DTO_PARAM),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
643
SR(DSCCLK_DTO_CTRL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
644
SR(DCCG_GATE_DISABLE_CNTL),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
645
SR(DCCG_GATE_DISABLE_CNTL2),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
646
SR(DCCG_GATE_DISABLE_CNTL3),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
647
SR(DCCG_GATE_DISABLE_CNTL4),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
648
SR(DCCG_GATE_DISABLE_CNTL5),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
649
SR(DCCG_GATE_DISABLE_CNTL6),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
650
SR(SYMCLKA_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
651
SR(SYMCLKB_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
652
SR(SYMCLKC_CLOCK_ENABLE),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
653
SR(SYMCLKD_CLOCK_ENABLE)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2194
FW_WM(srwm, SR) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
3671
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3711
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
681
reg |= FW_WM(wm, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
814
FW_WM(wm->sr.plane, SR) |
sys/dev/pci/drm/i915/display/i9xx_wm.c
864
FW_WM(wm->sr.plane, SR) |
