sys/dev/pci/drm/i915/display/intel_sprite.c

858

intel_de_write_fw(display, SPRCTL(pipe), sprctl);

sys/dev/pci/drm/i915/display/intel_sprite.c

872

intel_de_write_fw(display, SPRCTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1324

info->ctrl_reg = SPRCTL(info->pipe);

sys/dev/pci/drm/i915/gvt/display.c

205

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

519

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

sys/dev/pci/drm/i915/gvt/handlers.c

1057

if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

203

MMIO_D(SPRCTL(PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

216

MMIO_D(SPRCTL(PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

229

MMIO_D(SPRCTL(PIPE_C));