sys/dev/pci/drm/i915/display/intel_display_power.c

1216

intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

712

intel_de_write(display, SPLL_CTL, hw_state->spll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

713

intel_de_posting_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

738

intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

739

intel_de_posting_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

784

val = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

408

u32 ctl = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/gvt/handlers.c

491

switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {

sys/dev/pci/drm/i915/gvt/handlers.c

503

vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

495

MMIO_D(SPLL_CTL);