SOUTH_DSPCLK_GATE_D
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
MMIO_D(SOUTH_DSPCLK_GATE_D);