sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

280

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

281

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

282

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

283

SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

284

SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

285

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

286

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

287

SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

288

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

289

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

290

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

291

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

292

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

293

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

294

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

295

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

296

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

297

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

298

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

299

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

300

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

301

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

302

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

303

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

304

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

305

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

306

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

307

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

308

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

309

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

310

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

311

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

312

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

313

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

314

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

315

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

316

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

317

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

318

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

319

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

320

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

321

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

322

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

323

SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

324

SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

325

SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

326

SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

327

SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

328

SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

329

SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

330

SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

331

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

332

SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

333

SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

334

SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

335

SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

336

SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

337

SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

338

SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

339

SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

340

SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

341

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

342

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

343

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

344

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

345

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

346

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

347

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

348

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

349

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

350

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

351

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

352

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

353

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

354

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

355

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

356

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

357

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

358

SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

359

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

360

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

361

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

362

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

363

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

364

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

365

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

366

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

367

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

368

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

369

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

371

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

373

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

374

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

375

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

376

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

381

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

382

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

383

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

384

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

385

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

386

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

387

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

388

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

389

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

390

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

391

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

392

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

393

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

394

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

395

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

396

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

397

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

398

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

399

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

400

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

401

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

402

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

403

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

404

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

405

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

406

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

407

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

408

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

409

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

410

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

411

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

412

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

413

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

414

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

415

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

416

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

417

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

418

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

419

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

421

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

422

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

423

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

424

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

425

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

426

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

427

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

428

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

433

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

434

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

435

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

436

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

437

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

438

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

439

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

440

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

441

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

442

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

443

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

444

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

445

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

446

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

447

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

448

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

449

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

450

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

451

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

452

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

453

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

454

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

455

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

457

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

458

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

459

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

460

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

461

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

462

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

463

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

464

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

465

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

466

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

467

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

468

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

469

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

470

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

471

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

472

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

473

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

474

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

475

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

476

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

477

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

478

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

479

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

480

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

125

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

126

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

127

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

128

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

129

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

130

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

131

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

132

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

133

SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

134

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

135

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

136

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

137

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

138

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

139

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

140

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

141

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

142

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

143

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

144

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

145

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

146

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

147

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

148

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

149

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

150

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

151

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

152

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

153

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

154

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

155

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

156

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

157

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

158

SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

159

SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

160

SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

161

SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

162

SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

163

SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

164

SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

165

SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

166

SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

167

SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

168

SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

169

SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

170

SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

171

SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

172

SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

173

SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

174

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

175

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

176

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

177

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

178

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

179

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

180

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

181

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

183

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

184

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

185

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

186

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

187

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

188

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

189

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

190

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

192

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

193

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

194

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

195

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

196

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

197

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

202

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

203

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

204

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

205

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

206

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

207

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

208

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

209

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

210

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

211

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

212

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

213

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

214

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

215

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

216

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

217

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

218

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

219

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

220

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

221

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

222

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

223

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

224

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

225

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

226

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

227

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

228

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

229

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

230

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

231

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

232

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

233

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

234

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

235

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

236

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

237

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

238

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

239

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

240

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

242

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

243

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

244

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

245

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

246

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

247

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

248

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

249

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

254

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

255

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

256

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

257

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

258

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

259

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

260

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

261

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

262

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

263

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

264

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

265

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

266

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

267

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

268

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

269

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

270

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

271

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

272

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

273

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

274

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

275

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

276

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

277

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

278

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

280

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

281

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

282

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

283

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

284

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

285

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

286

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

287

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

288

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

289

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

290

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

291

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

292

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

293

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

294

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

295

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

100

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

101

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

102

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

103

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

104

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

105

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

106

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

107

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

108

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

109

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

110

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

111

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

112

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

113

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

114

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

115

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

116

SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

117

SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

118

SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

119

SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

120

SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

121

SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

122

SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

123

SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

124

SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

125

SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

126

SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

127

SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

128

SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

129

SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

130

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

131

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

132

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

133

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

134

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

135

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

136

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

137

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

138

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

140

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

141

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

142

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

143

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

144

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

145

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

146

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

147

SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

149

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

150

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

151

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

152

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

157

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

158

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

159

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

160

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

161

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

162

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

163

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

164

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

165

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

166

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

167

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

168

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

169

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

170

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

171

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

172

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

173

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

174

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

175

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

176

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

177

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

178

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

179

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

180

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

181

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

182

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

183

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

184

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

185

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

186

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

187

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

188

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

189

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

190

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

191

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

192

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

193

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

194

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

195

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

197

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

198

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

199

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

200

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

201

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

202

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

203

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

204

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

209

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

210

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

211

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

212

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

213

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

214

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

215

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

216

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

217

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

218

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

219

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

220

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

221

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

222

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

223

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

224

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

225

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

226

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

227

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

228

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

229

SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

230

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

231

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

232

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

233

SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

235

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

236

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

237

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

238

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

239

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

240

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

241

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

242

SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

243

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

244

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

245

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

246

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

247

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

248

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

249

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

250

SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

86

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

87

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

88

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

89

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

90

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

91

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

93

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

94

SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

95

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

96

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

97

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

98

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

99

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

154

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

155

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

156

SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

157

SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

158

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

159

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

160

SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

161

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

162

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

163

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

164

SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

165

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

166

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

167

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

168

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

169

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

170

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

171

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

172

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

173

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

174

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

175

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

176

SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

177

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

178

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

179

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

180

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

181

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

182

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

183

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

184

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

185

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

186

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

187

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

188

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

189

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

190

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

191

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

192

SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

193

SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

194

SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

195

SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

196

SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

197

SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

198

SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

199

SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

200

SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

201

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

202

SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

203

SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

204

SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

205

SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

206

SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

207

SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

208

SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

209

SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

210

SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

211

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

212

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

213

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

214

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

215

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

216

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

217

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

218

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

219

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

220

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

221

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

222

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

223

SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

224

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

225

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

226

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

227

SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

229

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

230

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

231

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

232

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

234

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

235

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

236

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

237

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

238

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

239

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

240

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

241

SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

242

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

243

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

244

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

245

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

246

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

247

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

248

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

249

SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

250

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

251

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

252

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

253

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

254

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

255

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

256

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

257

SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

262

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

263

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

264

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

265

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

266

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

267

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

268

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

269

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

270

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

271

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

272

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

273

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

274

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

275

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

276

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

277

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

278

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

279

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

280

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

281

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

282

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

283

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

284

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

285

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

286

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

287

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

288

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

289

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

290

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

291

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

292

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

293

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

294

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

295

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

296

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

297

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

298

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

299

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

300

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

301

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

302

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

303

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

304

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

305

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

306

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

100

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

101

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

102

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

103

SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

104

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

105

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

106

SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

107

SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

109

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

110

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

111

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

112

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

117

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

118

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

119

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

120

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

121

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

122

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

123

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

124

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

125

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

126

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

127

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

128

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

129

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

130

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

131

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

132

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

133

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

134

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

135

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

136

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

137

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

138

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

139

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

140

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

141

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

142

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

143

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

144

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

145

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

146

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

147

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

148

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

149

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

150

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

151

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

152

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

153

SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

154

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

155

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

156

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

157

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

158

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

159

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

160

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

161

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

68

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

69

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

70

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

71

SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

72

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

73

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

74

SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

75

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

76

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

77

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

78

SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

79

SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

80

SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

81

SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

82

SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

83

SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

84

SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

85

SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

86

SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

87

SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

88

SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

89

SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

90

SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

91

SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

92

SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

93

SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

94

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

95

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

96

SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

97

SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

98

SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

99

SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

36

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

37

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

38

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

39

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

40

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

41

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

42

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

43

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

44

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

45

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

46

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

47

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

48

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

40

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

41

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

42

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

43

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

44

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

45

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

46

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

47

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

48

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

49

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

50

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

51

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

52

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

38

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

39

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

40

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

41

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

42

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

43

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

44

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

45

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

46

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

47

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

48

SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

49

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

50

SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

40

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

41

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

42

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

43

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

44

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

45

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

46

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

47

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

48

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

49

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

50

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

51

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

52

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

63

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

64

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

65

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

66

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

67

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

68

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

69

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

70

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

71

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

72

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

73

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

74

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

75

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

76

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

77

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

78

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

79

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

80

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

81

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

82

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

83

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

84

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

85

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

86

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

87

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

88

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

89

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

90

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

91

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

92

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

93

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

94

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

95

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

50

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

51

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

52

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

53

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

54

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

55

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

56

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

57

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

58

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

59

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

60

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

61

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

62

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

38

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

39

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

40

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

41

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

42

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

43

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

44

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

45

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

46

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

47

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

48

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

49

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

50

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

59

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

60

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

61

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

62

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

63

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

64

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

65

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

66

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

67

SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

68

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

69

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

70

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

71

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

72

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

73

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

74

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

75

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

76

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

77

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

78

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

79

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

80

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

81

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

82

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

83

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

84

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

85

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

86

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

87

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

88

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

89

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

90

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

91

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

92

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

93

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

94

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

95

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

96

SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

100

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

101

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

102

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

103

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

104

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

105

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

106

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

107

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

108

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

109

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

110

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

111

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

112

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

113

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

114

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

115

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

116

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

117

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

118

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

119

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

76

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

77

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

78

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

80

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

81

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

83

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

84

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

85

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

86

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

87

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

88

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

89

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

90

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

91

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

93

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

94

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

95

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

96

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

97

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

98

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

99

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

52

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

53

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

54

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

55

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

56

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

57

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

58

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

59

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

60

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

61

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

62

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

63

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

64

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

65

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

66

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

67

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

68

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

69

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

70

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

71

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

72

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

73

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

74

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

75

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

76

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

77

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

78

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

79

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

80

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

81

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

82

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

83

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

84

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

85

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

86

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

87

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

88

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

89

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

90

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

91

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

92

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

93

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

94

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

95

SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

100

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

101

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

102

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

103

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

104

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

105

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

106

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

107

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

108

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

63

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

64

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

65

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

66

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

67

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

68

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

69

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

70

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

71

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

72

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

73

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

74

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

75

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

76

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

77

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

78

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

80

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

81

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

83

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

84

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

85

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

86

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

87

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

88

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

89

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

90

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

91

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

93

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

94

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

95

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

96

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

97

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

98

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

99

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

100

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

101

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

102

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

103

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

104

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

105

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

106

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

107

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

108

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

109

SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

64

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

65

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

66

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

67

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

68

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

69

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

70

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

71

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

72

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

73

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

74

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

75

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

76

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

77

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

78

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

79

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

80

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

81

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

82

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

83

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

84

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

85

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

86

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

87

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

88

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

89

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

90

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

91

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

92

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

93

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

94

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

95

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

96

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

97

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

98

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

99

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

100

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

101

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

102

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

103

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

104

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

105

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

106

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

107

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

108

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

109

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

110

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

111

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

112

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

113

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

114

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

115

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

116

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

117

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

64

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

65

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

66

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

67

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

68

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

69

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

70

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

71

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

72

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

73

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

74

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

75

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

76

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

77

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

78

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

80

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

81

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

83

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

84

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

85

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

86

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

87

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

88

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

89

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

90

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

91

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

93

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

94

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

95

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

96

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

97

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

98

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

99

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

100

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

101

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

102

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

103

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

104

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

105

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

106

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

107

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

108

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

109

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

110

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

111

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

112

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

113

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

114

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

115

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

116

SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

117

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

63

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

64

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

65

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

66

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

67

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

68

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

69

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

70

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

71

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

72

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

73

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

74

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

75

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

76

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

77

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

78

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

80

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

81

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

83

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

84

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

85

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

86

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

87

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

88

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

89

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

90

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

91

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

93

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

94

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

95

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

96

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

97

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

98

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

99

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

49

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

50

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

51

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

52

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

53

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

54

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

55

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

56

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

57

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

59

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

60

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

61

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

62

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

63

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

64

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

68

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

69

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

70

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

71

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

74

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

75

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

77

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

78

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

79

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

80

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

59

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

60

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

61

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

62

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

63

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

64

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

68

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

69

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

70

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

71

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

74

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

75

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

77

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

78

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

79

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

80

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

82

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

83

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

84

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

85

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

86

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

87

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

88

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

89

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

90

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

60

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

61

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

62

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

63

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

64

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

67

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

68

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

69

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

70

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

71

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

73

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

74

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

75

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

77

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

78

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

79

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

80

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

82

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

83

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

84

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

85

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

86

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

87

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

88

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

89

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

90

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

91

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

92

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

93

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

68

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

69

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

70

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

71

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

74

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

75

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

77

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

78

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

79

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

80

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

82

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

83

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

84

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

85

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

86

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

87

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

88

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

89

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

90

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

91

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

92

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

93

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

94

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

95

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

96

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

97

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

61

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

62

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

63

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

64

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

68

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

69

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

70

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

71

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

74

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

75

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

76

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

77

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

78

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

79

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

80

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

82

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

83

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

84

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

85

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

86

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

87

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

88

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

89

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

51

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

52

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

53

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

54

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

55

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

56

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

61

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

62

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

63

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

64

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

68

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

69

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

70

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

71

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

74

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

75

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

76

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

77

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

78

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

79

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

80

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

81

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

82

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

83

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

61

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

62

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

63

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

64

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

68

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

69

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

70

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

71

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

74

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

75

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

76

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

77

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

78

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

79

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

80

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

81

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

82

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

83

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

84

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

85

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

86

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

87

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

88

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

89

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

41

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

42

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

43

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

44

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

45

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

46

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

47

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

48

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

49

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

50

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

51

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

52

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

53

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

54

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

55

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

56

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

61

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

62

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

63

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

64

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

68

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

69

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

70

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

71

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

44

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

45

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

46

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

47

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

48

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

49

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

50

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

51

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

52

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

53

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

54

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

55

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

56

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

58

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

61

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

62

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

63

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

64

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

66

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

68

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

69

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

70

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

71

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

72

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

74

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)