Symbol: SMU__NUM_SCLK_DPM_STATE
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2866
if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3276
if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
157
SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h
41
#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h
61
#define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h
179
SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h
109
#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h
166
SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h
105
#define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h
150
SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h
134
#define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h
179
SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h
55
#define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h
192
SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h
235
SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h
224
SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];
sys/dev/pci/drm/radeon/kv_dpm.c
2607
if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
sys/dev/pci/drm/radeon/kv_dpm.c
2629
if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
sys/dev/pci/drm/radeon/kv_dpm.h
131
SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
sys/dev/pci/drm/radeon/smu7.h
41
#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
sys/dev/pci/drm/radeon/smu7_discrete.h
226
SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
sys/dev/pci/drm/radeon/smu7_fusion.h
224
SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];