ADDR_FIX_1
F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
ADDR_FIX_1(2), 8, NULL},
{"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
ADDR_FIX_1(3), 8, NULL},
ADDR_FIX_1(4), 8, NULL},
ADDR_FIX_1(4), 8, NULL},
D_ALL, ADDR_FIX_1(4), 8, NULL},
F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
D_ALL, ADDR_FIX_1(4), 8, NULL},
F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
D_ALL, ADDR_FIX_1(2), 8, NULL},
D_ALL, ADDR_FIX_1(2), 8, NULL},
R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
ADDR_FIX_1(1), 8, NULL},
ADDR_FIX_1(1), 8, NULL},
R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
#define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
#define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
#define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
#define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))