sys/arch/arm64/dev/smmu.c

1687

if (smmu_v3_read_4(sc, SMMU_V3_CR0) & SMMU_V3_CR0_SMMUEN) {

sys/arch/arm64/dev/smmu.c

1702

smmu_v3_write_ack(sc, SMMU_V3_CR0, SMMU_V3_CR0ACK, 0);

sys/arch/arm64/dev/smmu.c

1754

smmu_v3_write_ack(sc, SMMU_V3_CR0, SMMU_V3_CR0ACK,

sys/arch/arm64/dev/smmu.c

1767

smmu_v3_write_ack(sc, SMMU_V3_CR0, SMMU_V3_CR0ACK,

sys/arch/arm64/dev/smmu.c

1768

smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_EVENTQEN);

sys/arch/arm64/dev/smmu.c

1777

smmu_v3_write_ack(sc, SMMU_V3_CR0, SMMU_V3_CR0ACK,

sys/arch/arm64/dev/smmu.c

1778

smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_PRIQEN);

sys/arch/arm64/dev/smmu.c

1791

smmu_v3_write_ack(sc, SMMU_V3_CR0, SMMU_V3_CR0ACK,

sys/arch/arm64/dev/smmu.c

1792

smmu_v3_read_4(sc, SMMU_V3_CR0) | SMMU_V3_CR0_SMMUEN);