SH_
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
_reg_bclr_1(SH_(TSTR), TSTR_STR##x); \
_reg_write_4(SH_(TCNT ## x), 0xffffffff); \
_reg_bset_1(SH_(TSTR), TSTR_STR##x); \
(0xffffffff - _reg_read_4(SH_(TCNT ## x)))
_reg_write_2(SH_(TCR0), 0);
_reg_write_2(SH_(TCR1), 0);
_reg_write_2(SH_(TCR2), 0);
_reg_write_1(SH_(RCR1), 0);
_reg_write_1(SH_(TSTR), 0);
_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
_reg_write_2(SH_(TCR0),
_reg_bset_1(SH_(RCR2), SH_RCR2_ENABLE);
_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
_reg_write_1(SH_(TSTR), 0);
return 0xffffffff - _reg_read_4(SH_(TCNT2));
_reg_bclr_1(SH_(TSTR), TSTR_STR0);
_reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16);
_reg_write_2(SH_(TCR0), TCR_UNIE |
_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
_reg_bset_1(SH_(TSTR), TSTR_STR0);
_reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4);
_reg_write_4(SH_(TCOR1), 0xffffffff);
_reg_write_2(SH_(TCR2), TCR_TPSC_P4);
_reg_write_4(SH_(TCOR2), 0xffffffff);
_reg_bset_1(SH_(TSTR), TSTR_STR2);
_reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);
uint8_t r = _reg_read_1(SH_(RCR1));
_reg_write_1(SH_(RCR1), r);
#define RTCGET(x, y) dt->dt_ ## x = FROMBCD(_reg_read_1(SH_(R ## y ## CNT)))
} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);
r = _reg_read_1(SH_(RCR2));
_reg_write_1(SH_(RCR2), r);
#define RTCSET(x, y) _reg_write_1(SH_(R ## x ## CNT), TOBCD(dt->dt_ ## y))
_reg_write_1(SH_(RCR2), r | SH_RCR2_START);
_reg_write_2(SH_(BBRA), 0); /* disable break */
_reg_write_4(SH_(BARA), 0); /* break address */
_reg_write_1(SH_(BASRA), 0); /* break ASID */
_reg_write_1(SH_(BAMRA), 0x07); /* break always */
_reg_write_2(SH_(BRCR), 0x400); /* break after each execution */
printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));
_reg_bclr_1(SH_(TSTR), TSTR_STR1);
_reg_write_4(SH_(TCNT1), 0);
_reg_bset_1(SH_(TSTR), TSTR_STR1);
_reg_bclr_1(SH_(TSTR), TSTR_STR1);
_reg_bclr_2(SH_(TCR1), TCR_UNF);
_reg_write_2(SH_(BBRB), 0);
_reg_write_2(SH_(BBRB), 0);
_reg_write_4(SH_(BARB), nproc->p_md.md_regs->tf_spc);
_reg_write_1(SH_(BASRB), pm_asid);
_reg_write_1(SH_(BAMRB), 0);
_reg_write_2(SH_(BRCR), 0x0040);
_reg_write_2(SH_(BBRB), 0x0014);
_reg_write_2(SH_(BBRB), 0);
_reg_write_4(SH_(PTEH), asid);
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
int tra = _reg_read_4(SH_(TRA));