sys/dev/pci/drm/amd/amdgpu/cik.c

1052

{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1054

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1056

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1096

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1098

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1101

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1103

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

49

SDMA0_REGISTER_OFFSET,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

879

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

882

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

885

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

900

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

903

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

910

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

913

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1000

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1002

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

61

SDMA0_REGISTER_OFFSET,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

951

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

953

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

995

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

997

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1333

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1335

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1338

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1340

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

76

SDMA0_REGISTER_OFFSET,

sys/dev/pci/drm/amd/amdgpu/vi.c

675

{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},

sys/dev/pci/drm/radeon/cik.c

165

case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):

sys/dev/pci/drm/radeon/cik.c

3327

WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/pci/drm/radeon/cik.c

4812

RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));

sys/dev/pci/drm/radeon/cik.c

4866

tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

4954

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

4956

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/radeon/cik.c

5157

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

5159

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/radeon/cik.c

5512

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

5513

WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6159

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/pci/drm/radeon/cik.c

6162

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

6165

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/radeon/cik.c

6180

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

6183

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/radeon/cik.c

6190

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

6193

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/pci/drm/radeon/cik.c

6863

tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

6864

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/radeon/cik.c

7048

dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

7219

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);

sys/dev/pci/drm/radeon/cik_sdma.c

116

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

260

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

310

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

342

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

375

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

483

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik_sdma.c

485

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));

sys/dev/pci/drm/radeon/cik_sdma.c

486

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/pci/drm/radeon/cik_sdma.c

501

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik_sdma.c

503

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));

sys/dev/pci/drm/radeon/cik_sdma.c

504

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/pci/drm/radeon/cik_sdma.c

514

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik_sdma.c

71

reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik_sdma.c

95

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;