sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

373

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

382

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1001

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1012

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1017

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

996

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1334

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1339

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1350

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1355

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

581

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

583

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

592

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

594

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1012

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1415

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2067

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1600

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1686

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

630

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

794

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

797

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1509

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1592

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

489

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

641

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

644

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1602

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

437

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1536

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

sys/dev/pci/drm/radeon/cik.c

6863

tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

6864

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/radeon/cik.c

6865

tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

6866

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/pci/drm/radeon/cik.c

7048

dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

7049

dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/pci/drm/radeon/cik.c

7219

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);

sys/dev/pci/drm/radeon/cik.c

7220

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);

sys/dev/pci/drm/radeon/cik_sdma.c

313

value = RREG32(SDMA0_CNTL + reg_offset);

sys/dev/pci/drm/radeon/cik_sdma.c

318

WREG32(SDMA0_CNTL + reg_offset, value);