Symbol: AVIVO_D1GRPH_UPDATE
sys/dev/pci/drm/radeon/rs600.c
123
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
128
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
144
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/pci/drm/radeon/rs600.c
152
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
160
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/pci/drm/radeon/rv515.c
336
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
339
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
386
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
389
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
397
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv770.c
804
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rv770.c
809
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
832
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/pci/drm/radeon/rv770.c
840
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
848
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &