sys/dev/pci/drm/radeon/r600.c

1593

if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {

sys/dev/pci/drm/radeon/radeon_device.c

702

reg = RREG32(AVIVO_D1CRTC_CONTROL) |

sys/dev/pci/drm/radeon/rs600.c

333

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

335

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs600.c

351

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/rs600.c

353

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/rs600.c

98

if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))

sys/dev/pci/drm/radeon/rv515.c

280

crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;

sys/dev/pci/drm/radeon/rv515.c

283

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

sys/dev/pci/drm/radeon/rv515.c

288

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/pci/drm/radeon/rv515.c

301

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

sys/dev/pci/drm/radeon/rv515.c

303

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/pci/drm/radeon/rv515.c

422

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

sys/dev/pci/drm/radeon/rv515.c

424

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);