RW
if (RW) {
{ NVRAM_ADDR, NVRAM_SPACE, RW },
{ NVRAM_ADDR_88K2, PAGE_SIZE, RW },
{ OBIO_PIO0_BASE, PAGE_SIZE, RW },
{ OBIO_PIO1_BASE, PAGE_SIZE, RW },
{ OBIO_SIO, PAGE_SIZE, RW },
{ OBIO_TAS, PAGE_SIZE, RW },
{ OBIO_CLOCK0, PAGE_SIZE, RW },
{ INT_ST_MASK0, PAGE_SIZE, RW },
{ SOFT_INT0, PAGE_SIZE, RW },
{ SOFT_INT_FLAG0, PAGE_SIZE, RW },
{ RESET_CPU0, PAGE_SIZE, RW },
{ TRI_PORT_RAM, TRI_PORT_RAM_SPACE, RW },
{ EXT_A_ADDR, EXT_A_SPACE, RW },
{ EXT_B_ADDR, EXT_B_SPACE, RW },
{ PC_BASE, PC_SPACE, RW },
{ BMAP_RFCNT, PAGE_SIZE, RW },
{ BMAP_BMSEL, PAGE_SIZE, RW },
{ BMAP_BMP, BMAP_BMAP0 - BMAP_BMP, RW, TRUE },
{ BMAP_BMAP0, BMAP_BMAP1 - BMAP_BMAP0, RW, TRUE },
{ BMAP_BMAP1, BMAP_BMAP2 - BMAP_BMAP1, RW, TRUE },
{ BMAP_BMAP2, BMAP_BMAP3 - BMAP_BMAP2, RW, TRUE },
{ BMAP_BMAP3, BMAP_BMAP4 - BMAP_BMAP3, RW, TRUE },
{ BMAP_BMAP4, BMAP_BMAP5 - BMAP_BMAP4, RW, TRUE },
{ BMAP_BMAP5, BMAP_BMAP6 - BMAP_BMAP5, RW, TRUE },
{ BMAP_BMAP6, BMAP_BMAP7 - BMAP_BMAP6, RW, TRUE },
{ BMAP_BMAP7, BMAP_FN - BMAP_BMAP7, RW, TRUE },
{ BMAP_FN, PAGE_SIZE, RW },
{ BMAP_FN0, PAGE_SIZE, RW },
{ BMAP_FN1, PAGE_SIZE, RW },
{ BMAP_FN2, PAGE_SIZE, RW },
{ BMAP_FN3, PAGE_SIZE, RW },
{ BMAP_FN4, PAGE_SIZE, RW },
{ BMAP_FN5, PAGE_SIZE, RW },
{ BMAP_FN6, PAGE_SIZE, RW },
{ BMAP_FN7, PAGE_SIZE, RW },
{ BMAP_PALLET0, PAGE_SIZE, RW },
{ BMAP_PALLET1, PAGE_SIZE, RW },
{ BMAP_PALLET2, PAGE_SIZE, RW },
{ BOARD_CHECK_REG, PAGE_SIZE, RW },
{ BMAP_CRTC, PAGE_SIZE, RW },
{ SCSI_ADDR, PAGE_SIZE, RW },
{ LANCE_ADDR, PAGE_SIZE, RW },
reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_TX_END_DATA_START,
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);
reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10);
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);
reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask);
reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask);
reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask);
reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181);
reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361);
reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400);
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100);
reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]);
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC,
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND,
reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->gain1[chain]);
reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->trainpow);
reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);
reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
reg = RW(reg, AR_RXBP_THRESH_HP, 1);
reg = RW(reg, AR_RXBP_THRESH_LP, 1);
reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_TX_END_DATA_START,
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
reg = RW(reg, AR_PHY_TX_GAIN, txgain);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,
reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);
reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);
reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);
reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);
reg = RW(reg, AR9271_AN_RF2G4_DB2, db2[0]);
reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);
reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);
reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);
reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);
reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);
reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);
reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);
reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);
reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);
reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);
reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_TX_END_PA_ON,
reg = RW(reg, AR_PHY_TX_END_DATA_START,
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);
reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);
reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);
reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);
reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,
reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);
reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);
reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);
reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);
reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
reg = RW(reg, AR_RSSI_THR_BM_THR, 10);
reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);
reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,
reg = RW(reg, AR_TIME_OUT_ACK, ackto * athn_clock_rate(sc));
reg = RW(reg, AR_TIME_OUT_CTS, ctsto * athn_clock_rate(sc));
reg = RW(reg, AR_USEC_USEC, clockrate - 1);
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]);
reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_POWER_CCK2]);
reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_POWER_CCK55]);
reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_POWER_CCK11]);
reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_POWER_CCK1]);
reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_POWER_CCK2]);
reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_POWER_CCK55]);
reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_POWER_CCK11]);
RW(rf_ac[i], R92C_RF_AC_MODE,
reg = RW(reg, R92C_RRSR_RATE_BITMAP,
reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);
RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
reg = RW(reg, R92C_EFUSE_TEST_SEL, 0);
reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates);
GCVM_L2_PROTECTION_FAULT_STATUS, RW));
GCVM_L2_PROTECTION_FAULT_STATUS_LO32, RW));
GCVM_L2_PROTECTION_FAULT_STATUS, RW));
GCVM_L2_PROTECTION_FAULT_STATUS, RW));
GCVM_L2_PROTECTION_FAULT_STATUS, RW));
GCVM_L2_PROTECTION_FAULT_STATUS, RW));
rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS, RW);
MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW);
reg = RW(reg, R92C_MCUFWDL_PAGE, page);
reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr);
reg = RW(reg, R92C_MCUFWDL_PAGE, page);
reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc);
RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6));
RW(reg, R92C_AFE_CTRL3_ADDR, xtal | xtal << 6));
mode = RW & ~umask(RW);
long RW; /* open LP for reading and writing */
extern long RW; /* open LP for reading and writing */
RW = (cgetcap(bp, "rw", ':') != NULL);
pfd = open(LP, RW ? O_RDWR : O_WRONLY);