sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

603

*data++ = RREG32_NO_KIQ(mmMM_DATA);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1184

return RREG32_NO_KIQ(offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

52

return RREG32_NO_KIQ(0xc040) == 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8306

pre_data = RREG32_NO_KIQ(reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5599

pre_data = RREG32_NO_KIQ(reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3965

data = RREG32_NO_KIQ(reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5551

data = RREG32_NO_KIQ(mmRLC_SPM_VMID);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5161

data = RREG32_NO_KIQ(reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1676

pre_data = RREG32_NO_KIQ(reg);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

313

inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

319

RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

290

inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

296

RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

913

RREG32_NO_KIQ(req);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

38

RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

447

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

465

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

496

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

418

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

433

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

465

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

418

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

433

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

464

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

140

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

182

RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

243

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

331

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

58

return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

68

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

226

RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

237

RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

304

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

398

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

57

return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

67

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

325

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

330

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

339

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

347

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

358

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

374

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

379

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

395

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

405

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

504

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

537

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

427

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

441

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

472

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

356

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

371

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

402

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

437

wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

455

tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

487

v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);

sys/dev/pci/drm/amd/amdgpu/vi.c

304

(void)RREG32_NO_KIQ(mmPCIE_INDEX);

sys/dev/pci/drm/amd/amdgpu/vi.c

305

r = RREG32_NO_KIQ(mmPCIE_DATA);

sys/dev/pci/drm/amd/amdgpu/vi.c

316

(void)RREG32_NO_KIQ(mmPCIE_INDEX);

sys/dev/pci/drm/amd/amdgpu/vi.c

318

(void)RREG32_NO_KIQ(mmPCIE_DATA);

sys/dev/pci/drm/amd/amdgpu/vi.c

329

r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);